Project Laboratory IC Design

Vortragende/r (Mitwirkende/r)
Umfang4 SWS
SemesterSommersemester 2019
Stellung in StudienplänenSiehe TUMonline


Teilnahmekriterien & Anmeldung

Siehe TUMonlineYou need to (1) register in TUMonline and (2) show up on time at the first introductory class. Registration from 15th March to 22nd April 2019 at TUMonline A preliminary assignment of seats in the lab is done via the coordinated allocation mechanism of the EI department.. The available seats in the lab will be finally given to the students present at the first introductory class in the order of registration. If you are not present at this class, your seat will be given to someone on the waiting list, even if you initially had a seat in TUMOnline. Therefore, presence at the first class might even be advantageous for students on the waiting list.


At the end of the lab students are able to understand the HW design flows from system specification to system test. They are able to implement an IC design with VHDL, they gain experience in teamwork as well as the presentation of their work results.


The lab course addresses the development of a VLSI design as a team effort. During the project, students will encounter all steps of the IC development process. This starts with defining the architectures for both the system as a whole, as well as each individual module. The modules will be modeled in VHDL and have to be simulated before and after synthesis. If all components work according to the specification, they are integrated to form the entire system. A system simulation with appropriate stimuli should demonstrate the functionality of the design. At the end of the lab, each verified system will be ported onto a FPGA, where it may be tested in the real environment. The development task is dimensioned such that it cannot be solved by an individual student. Instead it must be solved in a team. The implementation of the design as a team effort with the necessary distribution of sub-functions among different team members shall demonstrate the problems often encountered with respect to deciding on common interfaces, distributing sub-tasks and coordinating the integration of the individual modules.

Inhaltliche Voraussetzungen

Basic knowledge of the hardware description language VHDL is expected and will not be taught in this lab! The previous successful participation in a VHDL Lab (e.g. HDL Design Lab, Praktikum VHDL, Systementwurf mit VHDL or HW/SW-Codesign) or experience from internships is recommended.

Lehr- und Lernmethoden

During the introductory lectures students are instructed in a teacher-centered style (with the opportunity for discussion and to ask questions). The lab is performed by the students' self-coordination assisted by a student tutor.

Studien-, Prüfungsleistung

The grades for the lab are combined from three components: - Oral presentation of the design and submodules: 30% - Written report (5 pages): 50% - System integration, implementation on the FPGA and system test: 20%

Empfohlene Literatur

- Z. Navabi, "VHDL - Analysis and Modelling of Digital Systems", McGraw Hill - P. Ashenden, "The VHDL Cookbook"