Lebenslauf
- 2008, Diploma in Electrical Engineering/Computer Engineering, RWTH Aachen, Germany
- 2010, Diploma in Business Admnistration and Economics, RWTH Aachen, Germany
- November 2010-February 2011, HiPEAC internship at ARM Research & Development, Cambridge, UK
Lehre
- Project Laboratory IC-Design (summer term 2010)
- Chip Multicore Processors
Supervised Theses
- Design and Implementation of the I/O interfaces of OpTiMSoC on the iRobot platform
(Interdisciplinary Project, Umbreen Sabir Mian, 2013) - Level 2 Caches in the Open Tiled Manycore System-on-Chip
(Research Practice, Robert Specht, 2013) - Snoop Cache Coherency of Level 1 Caches in Tiled Manycore-Processors
(Research Practice, Simon Schulze, 2013) - Infrastructure for Trace-Compression and Debugging
(Master Thesis, Philipp Wagner, 2012) - Debug Infrastructure via Cypress EZ-USB for OpTiMSoC
(Research Practice, Michael Tempelmeier, 2012) - Multicast in Network-on-Chip
(Master Thesis, Manuel Krause, 2012) - Design and Implementation of a Lean Runtime System for OpTiMSoC
(Interdisciplinary Project, Michael Faath and Daniel Lowinski, 2012) - Online Network-on-Chip Message Monitoring
(Bachelor Thesis, Sonja Chomyn and Andreas Bollwein, 2012) - Directory-based Cache Coherency for Tiled Manycore Architectures
(Master Thesis, Xiaoyu Pi, 2012) - Design and Development of a Toolbox for Application-specific Network-on-Chip
(Bachelor Thesis, Markus Göhrle, 2012) - Design and Implementation of a System Feedback Visualization Framework
(Interdisciplinary Project, Falco Cescolini, 2011) - Design and Implementation of a Platform Generator Tool
(Interdisciplinary Project, Daniel Thaler, 2011) - Multicore Performance Monitors
(Bachelor Thesis, Daniel Schneider, 2011) - Multicore UART Virtualization
(Bachelor Thesis, Hans-Christian Wild, 2011) - Implementing the Multicore Association Communication API
(Interdisciplinary Project, Johannes Ehm, 2010) - Implementation of Cache Coherene Protocols and Process Synchronization in Multicore Processors
(Master Thesis, Liang Chen, 2010) - Intelligent Hardware Support for Hybrid Message Passing in Tiled Multicore Architectures
(Master Thesis, Muhammad Aurang Zaib, 2010) - Prototyping an FPGA-based Multiprocessor System-on-Chip and Runtime System
(Master Thesis, Ravi Kumar Pujari, 2010)
Forschung
As member of the Munich Center for Advanced Computing in the project Multicore Architecture and Programming Model Co-Optimization (MAPCO), my research focus is on macro-architecture support for programming model and runtime systems.
Topics of research include:
- message passing support for efficient on-chip communication
- loosely-coupled manycore architectures
- novel memory hierarchies and memory management
- thread management and lightweight runtime systems
In a broader scope my interests are also in:
- design space exploration
- emerging manycore architectures
