Dipl.-Ing. Philipp Wagner

Research Associate

Technische Universität München
Department of Electrical and Computer Engineering
Chair for Integrated Systems
Arcisstr. 21
80290 München
Germany

Phone: +49.89.289.23858
Fax: +49.89.289.28323
Building: N1 (Theresienstr. 90)
Room: N2116
Email: philipp.wagner@tum.de

Teaching

Previous courses

 

Theses in my field of research might be possible even if they are not explicitly listed here. Please contact me if you have an idea!

Supervised Theses

  • Detecting Inefficiency Patterns in an Event Trace
    (Master Thesis, Felix Aumer, 2016)
  • Implementation of a Video Output Interface for an FPGA
    (Forschungspraxis, Christian Zoller, 2016)
  • Integration of Event-Based Trace Components Into Open SoC Debug
    (Forschungspraxis, Tim Fritzmann, 2016)
  • Implementation of a Camera Interface for an FPGA
    (Forschungspraxis, David Wagner, 2016)
  • Design and Implementation of an Intermediate Representation for a Diagnosis Script Compiler
    (Forschungspraxis, Julius Löckemann, 2016)
  • Implementation of a Hybrid Data Race Detector
    (Bachelor Thesis, Gerrit Noske, 2016)
  • Conversion of Intel Processor Trace Messages to Trace Events
    (Forschungspraxis, Juliano Raimundo, 2016)
  • Design and Implementation of a Debug Script Language for Manycore System on Chip
    (Master Thesis, Max Koenen, 2016)
  • Evaluation and Implementation of an Object Detection Algorithm for a Multi-Processor System-on-Chip
    (Bachelor Thesis, Maximilian Ulmer, 2016)
  • Design and Implementation of a Processor for Debug Data Analysis
    (Master Thesis, Ignacio Alonso, 2015)
  • FPGARunner: A Framework for Automated Test Execution on FPGAs
    (Forschungspraxis, Christoph Paa, 2015)
  • Integration of Ethernet Communication for GLIP using Xilinx lwip
    (Forschungspraxis, Christoph Weber, 2015)
  • Design and Implementation of a Trace-Based On-ChipDiagnosis Solution for Manycore System-on-Chip
    (Master Thesis, Markus Göhrle, 2015)
  • Integration of a PCIe backend into GLIP
    (Forschungspraxis, Sebastian Pfeiffer, 2014)
  • Integration of a JTAG backend into GLIP
    (Forschungspraxis, Jan Alexander Wessel, 2014)
  • Integration of a RIFFA 2.0 backend into GLIP
    (Forschungspraxis, Chun Zhang, 2014)
  • Evaluation of the Parallella Multicore SoC Board
    (Ingenieurspraxis, Julius Löckemann, 2014)
  • Evaluation of Instruction Trace Compression Algorithms for OpTiMSoC
    (Bachelor Thesis, Julia Müller, 2013)
  • Collection and Compression of Memory Traces for Manycore System-on-Chip
    (Bachelor Thesis, Christian Morgenstern, 2013)

Research Interests

I research methods for debugging and diagnosis for multi- and manycore system-on-chip (SoC). I focus on problems in the software and macroarchitecture layers.

Projects

Open Source Projects

  • OpTiMSoC
    Free and open building blocks for a SoC
  • GLIP: the Generic Logic Interfacing Library
    Simple, FIFO-based communication between FPGA and a PC
  • Open SoC Debug (OSD)
    Building blocks for your SoC debug infrastructure

I administer the Linux Deployment project for the automated installation and management of Linux (desktop) PCs within the faculty. Please contact me if you have any questions on that.

Publications