FlexPath - Network processor architectures with flexible data paths
Network Processors (NP) are programmable VLSI components, which are optimized for processing data packets in communication networks. Although different solutions are commercially available for different applications (e.g. access, edge, core network), a common characteristic are the high performance requirements. The FlexPath NP project investigates a new architecture for network processors based on an open SoC architecture with standard RISC processor cores. Some parts of the packet processing task are moved from the central processor cluster towards specific processing units near the ingress (receive side) and egress (transmit side) link interfaces. In addition, we propose a dynamically reconfigurable hardware unit that enables an application-optimized packet routing through the various functional entities in the NP that shall guarantee a better overall utilization of the existing processing resources and increase the system throughput. Packets with very simple processing requirements may bypass the CPU cluster and can be handled in hardware alone (AutoRoute). By directing IPSec traffic directly to dedicated hardware accelerators for decryption before sending them to the CPU can also relieve the processor cluster. The architecture shall demonstrate the applicability and performance of dynamically reconfigurable methods in high-end applications.
- Development of a new method for implementing dynamically reconfigurable processing paths in network processors that are optimized for the requirements of individual packet flows. In our context, the term packet flow refers to virtual connections on different layers of the OSI reference model.
- Implementation of the method on an open platform-based SoC architecture, reusing as many components as possible from existing intellectual property (IP) libraries. Currently, no NP architecture based on an open SoC platform with "conventional" RISC processors (e.g. PowerPC, MIPS, ARM) and standard on-chip bus systems and memory interfaces is known.
- Proving the feasibility and performance of the method and the proposed architecture by both functional system level simulation and implementation and measurements on our FPGA prototyping platform.
- Investigation of various load balancing strategies in homogeneous and heterogeneous multi-processor SoCs and their implementation with the reconfigurable elements in FlexPath NP.
- The FlexPath NP project was completed in fall 2009. The projects' final results have been published in a chapter in the following book: "Dynamically Reconfigurable Systems: Architectures, Design, Methods and Applications", Springer Verlag, December 2009, ISBN: 978-90-481-348
FlexPath was supported by the German Research Foundation (DFG) from 2005 until 2009 and has been associated with DFG's SPP1148 "Reconfigurable Computing Systems" program. Presentations of all projects may be accessed in the Colloquium section (in German only).
Hardware Support to Exploit Parallelism in Homogeneous and Heterogeneous Multi-Core Systems on Chip. Springer Verlag, 2010 mehr… BibTeX
An Application-aware Load Balancing Strategy for Network Processors. International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC), 2010 mehr… BibTeX
An Efficient Hardware Architecture for Packet Re-sequencing in Network Processor MPSoCs. 12th Euromicro Conference on Digital System Design (DSD), 2009 mehr… BibTeX
FlexPath NP- Flexible, Dynamically Reconfigurable Processing Paths in Network Processors. In: Dynamically Reconfigurable Systems, Architectures, Design, Methods and Applications. Springer, 2009 mehr… BibTeX
A Hardware Packet Resequencer Unit for Network Processors. Architecture of Computing Systems (ARCS) (Lecture Notes in Computer Science 4934), Springer, 2008, 85-97 mehr… BibTeX Volltext ( DOI )
FlexPath NP - A Network Processor Architecture with Flexible Processing Paths. International Symposium on System-on-Chip (SoC), 2008 mehr… BibTeX
A Processing Path Dispatcher in Network Processor MPSoCs. IEEE Transactions on VLSI Systems, IEEE, 2008, 1335-1345 mehr… BibTeX
Reconfigurable Processing Units vs. Reconfigurable Interconnects. Dagstuhl Seminar on Dynamically Reconfigurable Architectures, 2007 mehr… BibTeX
A Programmable Stream Processing Engine for Packet Manipulation in Network Processors. IEEE Computer Society Annual Symposium on VLSI, 2007 (ISVLSI '07), 2007 mehr… BibTeX
A Packet Classification Technique for On-Chip Processing Path Selection. Proceedings of the 5th Workshop on Application Specific Processors (WASP'07), 2007, pp 95-102 mehr… BibTeX
Simulated and Measured Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. Journal of Systems Architecture Volume 53 (Issue 10), 2007, pp 703-718 mehr… BibTeX Volltext ( DOI )
Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2006), 2006 mehr… BibTeX
FlexPath NP - A Network Processor Concept with Application-Driven Flexible Processing Paths. CODES+ISSS, 2005 mehr… BibTeX