MAPCO - Multicore Architecture and Programming Model Co-Optimization

Motivation and Targets

Future manycore processors will integrate hundreds of processor cores. A major challenge is efficient utilization of the processing power by applications. We thus propose the joint optimization of hardware architecture and programming models

We target at tile architectures, that are NoC-based architectures, with simple RISC cores at the compute nodes (so called tiles) and mixed distributed and shared memory layout. Prominent examples are Intel's SCC or the Tilera processors

Our primary focus is on

  • Threading support
  • Efficient communication and synchronization

Approach and Results

ACACES summer school 2010 poster

We propose hardware enablements to offload cores from the overhead of

  • Transparent Collective Operations. Reduce overhead of communication and synchronization of threads
  • Inter-tile Threading. Propose a fork-join thread model, explicit communication, HW support for thread handling 

Publikationen

  • 1/4
    Stefan Wallentowitz, Michael Tempelmeier, Thomas Wild, Andreas Herkersdorf: Network-on-Chip Protection Switching Techniques for Dependable Task Migration on an Open Source MPSoC Platform. edaWorkshop, 2014 mehr… BibTeX
  • 2/4
    Stefan Wallentowitz, Thomas Wild, Andreas Herkersdorf: HW-OSQM: Reducing the Impact of Event Signaling by Hardware-based Operating System Queue Manipulation. International Conference on Architecture of Computing Systems (ARCS), Springer, 2013, 280-291 mehr… BibTeX
  • 3/4
    Stefan Wallentowitz, Marcel Meyer, Thomas Wild, Andreas Herkersdorf: Accelerating Collective Communication in Message Passing on Manycore System-on-Chip. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XI), 2011 mehr… BibTeX
  • 4/4
    Andreas Herkersdorf, Andreas Lankes, Michael Meitinger, Rainer Ohlendorf, Stefan Wallentowitz, Thomas Wild, Johannes Zeppenfeld: Hardware Support to Exploit Parallelism in Homogeneous and Heterogeneous Multi-Core Systems on Chip. Springer Verlag, 2010 mehr… BibTeX