Sie befinden sich hier: Mitarbeiter / 

Akademischer Direktor
Theresienstr. 90, Gebäude N1, Raum N2120
walter.stechele@tum.de
Tel. 089 / 289-22515
Fax 089 / 289-28323


Short CV

Walter Stechele received the Dipl.-Ing. and Dr.-Ing. degrees in electrical engineering from the Technical University of Munich, Germany, in 1983 and 1988, respectively. In 1990 he joined Kontron Elektronik GmbH, a German electronic company, where he was responsible for the ASIC and PCB design department. Since 1993 he has been Academic Director at the Institute for Integrated Systems at the Technical University of Munich. His interests include digital video processing and VLSI design, with focus on system-on-chip design methodology, low power optimization, dynamic reconfiguration of FPGAs, and applications in video-based driver assistance.

 


Research Interests

Digital video processing and visual scene analysis
Dynamic reconfiguration of FPGAs
MPSoC architecture exploration and design methodology
Applications in automotive and driver assistance




Publications

  • C. Claus, R. Ahmed, F. Altenried, W. Stechele, "Towards rapid dynamic partial reconfiguration in video-based driver assistance systems", 6th International Symposium on Applied Reconfigurable Computing, ARC 2010, Bangkok, Thailand, March 17-19, 2010
  • M. May, N. Wehn, A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, D. Ziener, J. Teich, "A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip", DATE Conference 2010, Dresden, March 8-12, 2010
  • C. Claus, R. Huitl, J. Rausch, W. Stechele, "Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation", 19th International Conference on Field Programmable Logic and Applications (FPL09), Prague, Czech Republic, August 31 - September 2, 2009
  • C. Claus, A. Laika, L. Jia, W. Stechele, "High performance FPGA based optical flow calculation using the census transformation", The Intelligent Vehicles Symposium (IV'09), Xi'an, China, June 3-5, 2009
  • S. Han, A. Hutter, W. Stechele, "TOWARD CONTEXTUAL FORENSIC RETRIEVAL FOR VISUAL SURVEILLANCE", 10th International Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS), London, UK, May 6-8, 2009 (ext. Link...)
  • A. Bouajila, J. Zeppenfeld, A. Herkersdorf, W. Stechele, "Multi-Bit Error Protection", edaWorkshop, Dresden, May 26-28, 2009
  • A. Bouajila, T. Sommer, J. Zeppenfeld, W. Stechele, A. Herkersdorf, "A Fault-Tolerant Processor Architecture", ARCS 2009, Workshop „Dependability and Fault-Tolerance, Delft, March 10-13, 2009
  • A. Laika, A. Taruttis, W. Stechele, "SEGMENTATION THROUGH EDGE-LINKING - Segmentation for Video-based Driver Assistance Systems", IMAGAPP 2009 - International Conference on Imaging Theory and Applications, Lisabon, Portugal, February 5-8, 2009 (ext. Link...)
  • P. Zuber, O. Bahlous, T. Ilnseher, M. Ritter, W. Stechele, "Wire Topology Optimization for Low Power CMOS", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009
  • C. Claus, W. Stechele, M. Kovatsch, J. Angermeier, J. Teich, "A comparison of embedded reconfigurable video-processing architectures", Proceedings of the International Conference on Field Programmable Logic and Applications (FPL08), Heidelberg, Germany, September 8-10, 2008
  • C. Claus, B. Zhang, W. Stechele, L. Braun, M. Hübner, J. Becker, "A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput", Proceedings of the International Conference on Field Programmable Logic and Applications (FPL08), Heidelberg, Germany, September 8-10, 2008
  • J. Zeppenfeld, A. Bouajila, W. Stechele, A. Herkersdorf, "Learning Classifier Tables for Autonomic Systems on Chip", Lecture Notes in Informatics, Springer, Gesellschaft für Informatik, GI Jahrestagung, München, September 12, 2008, Vol. 134, p. 771-778
  • Z. Wang, A. Sanchez, A. Herkersdorf, W. Stechele, "Fast and Accurate Software Performance Estimation during High-Level Embedded System Design", edaworkshop, Hannover, Deutschland, May 6-7, 2008 (Download...)
  • C. Estermann, W. Stechele, R. Kutka, A. Hutter, "Luminance Correction in Stereo Correspondence Based Structure from Motion", 9th International Workshop on Image Analysis for Multimedia Interactive Services, WIAMIS, Klagenfurt, Austria, May 7-9, 2008
  • A. Herkersdorf, J. Zeppenfeld, A. Bouajila, W. Stechele, "Hardware-Supported Learning Classifier Tables in Autonomic Systems on Chip", Dagstuhl Seminar 08141, March 30 - April 4, 2008
  • J. Angermeier, U. Batzer, M. Majer, J. Teich, C. Claus, W. Stechele, "Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System", International Workshop on Applied Reconfigurable Computing (ARC2008), Imperial College London, U.K., March 26-28, 2008
  • N. Alt, C. Claus, W. Stechele, "Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments", Design, Automation & Test in Europe (DATE 2008), Munich, March 10-14, 2008 (Download...)
  • A. Laika, K. Gresser, W. Stechele, M. Walessa, "Universelle Objekt-Klassifikation mit MPEG-7 Deskriptoren", 2. Fachforum Kraftfahrzeugtechnik, Sensorik für Fahrerassistenzsysteme, September 27-28, 2007
  • C. Claus, W. Stechele, A. Herkersdorf, "Autovision-A Run-time Reconfigurable MPSoC Architecture for future Driver Assistance Systems", it - Information Technology Journal, Issue No. 3, June 20, 2007 (Download...) (ext. Link...)
  • W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld, D. Ziener, "Concepts for Autonomic Integrated Systems", eda-Workshop, Hannover, June 19-20, 2007
  • A. Laika, W. Stechele, "A review of different object recognition methods for the application in driver assistance systems", 8th International Workshop on Image Analysis for Multimedia Interactive Services, WIAMIS 2007, June 6-8, 2007
  • C. Claus, B. Zhang, M. Huebner, C. Schmutzler, J. Becker, W. Stechele, "An XDL-based busmacro generator for customizable communication interfaces for dynamically and partially reconfigurable systems", Workshop on Reconfigurable Computing Education at ISVLSI 2007, Porto Alegre, Brazil, May 12, 2007 (Download...) (ext. Link...)
  • M. Hübner, L. Braun, J. Becker, C. Claus, W. Stechele, "Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs", IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), pp. 41-46, Porto Alegre, Brazil, May 9-11, 2007
  • P. Zuber, T. Ilnseher, W. Stechele, "Crosscoupling power optimal wire spacing in quasilinear runtime", SPIE VLSI Circuits and Systems conference, SPIE Digital Library paper no. 6590-22, Maspalomoas, Spain, May, 2007
  • C. Claus, J. Zeppenfeld, W. Stechele, "Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance Systems", Proceedings of DATE 2007, Nice, France, April 16-20, 2007 (ext. Link...)
  • A. Herkersdorf, W. Stechele, "Exploitation of Reconfiguration in Advanced Applications Run-Time Reconfiguration for High Performance Video-based Driver Assistance and High-Speed IP Networking", DATE 2007 Tutorial on Reconfigurable Computing: Architectures, Tools and Applications, Nice, France, April, 16-20, 2007
  • W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld, D. Ziener, "Autonomic MPSoCs for Reliable Systems", GMM/GI/ITG Fachtagung Zuverlässigkeit und Entwurf, ZuD, March 27-28, Munich, Germany, 2007
  • C. Claus, J. Zeppenfeld, F. H. Müller, W. Stechele, "A new framework to accelerate VirtexII Pro dynamic partial self-reconguration", 14th Reconfigurable Architectures Workshop, Long Beach, CA, March 26-27, 2007 (ext. Link...)
  • W. Stechele, "AutoVision: A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance", ECSI Workshop on Reconfigurable Systems-on-Chip, Paris, January 18, 2007
  • M. Vuletic, P. Ienne, C. Claus, W. Stechele, "Multithreaded Virtual-Memory-Enabled Reconfigurable Hardware Accelerators", accepted for IEEE International Conference on Field Programmable Technology, FPT, Bangkok, Thailand, December 13-15, 2006
  • C. Claus, H. C. Shin, W. Stechele, "Tunnel Entrance Recognition for video-based Driver Assistance Systems", IWSSIP 2006, 13th International Conference on Systems, Signals and Image Processing, Budapest, Hungary, September 21-23, 2006 (Download...)
  • W. Stechele, "Dynamically Reconfigurable Systems-on-Chip for Video-based Driver Assistance", Dagstuhl Seminar Proceedings 06141 on Dynamically Reconfigurable Architectures, April 2-7, 2006
  • C. Claus, F. Müller, W. Stechele, "Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro devices", International Conference on Architecture of Computing Systems, ARCS 2006, in GI Lecture Notes in Informatics, Workshop on Dynamically Reconfigurable Systems, Frankfurt, March 16, 2006 (Download...)
  • W. Stechele, "Video Processing using Reconfigurable Hardware Acceleration for Driver Assistance", Workshop on Future Trends in Automotive Electronics and Tool Integration at DATE 2006, Munich, March 6-10, 2006
  • A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, A. Bernauer, O. Bringmann, W. Rosenstiel, "Organic Computing at the System on Chip Level", Proceedings of the IFIP International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2006). Springer, October, 2006
  • A. Bernauer, O. Bringmann, W. Rosenstiel, A. Bouajila, W. Stechele, A. Herkersdorf, "An Architecture for Runtime Evaluation of SoC Reliability", INFORMATIK 2006 - Informatik für Menschen, volume P-93 of GI-Edition - Lecture Notes in Informatics, Bonn, Köllen Verlag. to be published, September, 2006, pp. 177-185
  • A. Bouajila, A. Bernauer, A. Herkersdorf, W. Rosenstiel, O. Bringmann, W. Stechele, "Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoC", Yi Pan, Franz J. Rammig, Hartmut Schmeck, and Mauricio Solar, editors, 1st IFIP International Conf., on Biologically Inspired Cooperative Computing (BICC 2006), vol. 216, Springer, Boston, August, 2006, pp. 107-113
  • R. Denchev, W. Stechele, "An Experimentation Environment for MPEG-7 based Driver Assistance", Eurocon 2005, Belgrade, November 22-24, 2005
  • W. Stechele, S. Herrmann, "Reconfigurable Hardware Acceleration for Video-based Driver Assistance", Workshop on Hardware for Visual Computing, Tübingen, April 29, 2005
  • R. Medina Beltran de Otalora, S. Herrmann, W. Stechele, "An Efficient Approach for Fine-Tuning and Tracking of Face Objects", European Workshop on Image Analysis for Interactive Multimedia Services, WIAMIS 2005, Montreux/Switzerland, April 13-15, 2005
  • W. Stechele, L. Alvado Cárcel, S. Herrmann, J. Lidón Simón, "A Coprocessor for Accelerating Visual Information Processing", Design Automation and Test in Europe, DATE 2005, Munich, March 7-11, 2005
  • P. Zuber, P. Gritzmann, M. Ritter, W. Stechele, "The Optimal Wire Order for Low Power CMOS", International Workshop on Power And Timing Modeling, PATMOS-05, Leuven, September, 2005
  • P. Zuber, F. H. Müller, W. Stechele, "Optimization Potential of CMOS Power by Wire Spacing", Lecture Notes in Informatics, INFORMATIK-Live-05, Bonn, September, 2005
  • G. Lipsa, A. Herkersdorf, W. Rosenstiel, O. Bringmann, W. Stechele, "Towards a Framework and a Design Methodology for Autonomic SoC", International Conference on Autonomic Computing, ICAC-05, Seattle, June 13-16, 2005
  • P. Zuber, A. Windschiegl, R. Medina, W. Stechele, A. Herkersdorf, "Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization", Design, Automation & Test in Europe, DATE-05, Munich, March, 2005
  • W. Stechele, B. De Mey, "Training for SoC Designers: Today's Solutions for Tomorrow's Problems?", European Workshop on Microelectronics Education, EWME 2004, Lausanne, April 15-16, 2004
  • W. Stechele, S. Herrmann, A. Herkersdorf, "Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing", International Conference on Architecture of Computing Systems, ARCS 2004, Augsburg, Germany, March 23-26, 2004
  • W. Stechele, "Performance Optimization of Color Segmentation Algorithms", International Conference on Signal and Image Processing, SIP 2003, Honololu, August 13-15, 2003
  • W. Stechele, "VLSI architecture for MPEG-4 core profile video codec with accelerated bitstream processing", VLSI Circuits and Systems conference at SPIE's International Symposium on Microtechnologies for the New Millennium 2003, Maspalomas, Spain, May 19-21, 2003
  • S. Herrmann, H. Mooshofer, W. Stechele, "Processing in the MPEG-7 Reference Software using the AddressLib", European Workshop on Image Analysis for Multimedia Interactive Services, WIAMIS 2003, London, April 9-11, 2003
  • T. Mahnke, W. Stechele, M. Embacher, W. Hoeld, "Exploration of dual supply voltage logic synthesis in state-of-the-art ASIC design flows", URSI Kleinheubacher Tagung, Miltenberg, Germany, (published in "Advances in Radio Science - Kleinheubacher Berichte" at www.copernicus.org), September, 2002
  • T. Mahnke, S. Panenka, M. Embacher, W. Stechele, W. Hoeld, "Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness", IEEE Int. Conf. on Electronics, Circuits and Systems, Dubrovnik, Croatia, September, 2002
  • T. Mahnke, W. Stechele, M. Embacher, W. Hoeld, "Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis", IEEE Int. Conf. on Electronics, Circuits and Systems, Dubrovnik, Croatia, September, 2002
  • A. Windschiegl, T. Mahnke, M. Eiermann, W. Stechele, P. Zuber, "A wire load model considering metal layer properties", IEEE Int. Conf. on Electronics, Circuits and Systems, Dubrovnik, Croatia, September, 2002
  • M. Eiermann, W. Stechele, "Efficient power modeling techniques for combinational and sequential RTL macroblocks", IEEE Int. Conf. on Electronics, Circuits and Systems, Dubrovnik, Croatia, September, 2002
  • T. Mahnke, W. Stechele, W. Hoeld, "Dual supply voltage scaling in a conventional power-driven logic synthesis environment", Int. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sevilla, Spain, September, 2002
  • A. Windschiegl, P. Zuber, W. Stechele, "Exploiting metal layer characteristics for low-power routing", Int. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sevilla, Spain, September, 2002
  • M. Eiermann, W. Stechele, "Novel modeling techniques for RTL power estimation", Int. Symposium on Low Power Electronics and Design, Monterey, USA, August, 2002
  • A. Windschiegl, P. Zuber, W. Stechele, "A Wire Load Model for More Accurate Power Estimation", IEEE Int. Midwest Symposium on Circuits and Systems, Tulsa, USA, August, 2002
  • M. Eiermann, W. Stechele, "RTL Power Modeling and Estimation Based on Bit and Word Level Switching Properties", IEEE Int. Midwest Symposium on Circuits and Systems, Tulsa, USA, August, 2002
  • T. Mahnke, S. Panenka, M. Embacher, W. Stechele, W. Hoeld, "Optimizing power using advanced voltage scaling techniques in logic synthesis", The 2002 Int. Conf. on VLSI, Las Vegas, USA, June, 2002
  • T. Mahnke, S. Panenka, M. Embacher, W. Stechele, W. Hoeld, "Power optimization through dual supply voltage scaling using Power Compiler", Synopsys Users Group Meeting, Paris, France, March, 2002
  • U. Niedermeier, J. Heuer, A. Hutter, W. Stechele, A. Kaup, "An MPEG-7 Tool for Compression and Streaming of XML Data", Conference on Multimedia and Expo, ICME 2002, Lausanne, Switzerland, August 26-29, 2002
  • U. Niedermeier, J. Heuer, A. Hutter, W. Stechele, "MPEG-7 Binary Format for XML Data", Data Compression Conference, DCC 2002, Snowbird, Utah, April 2-4, 2002
  • K. Jacob, W. Stechele, "Adapting the MPEG-4 Video Verifier Model for Video Decoder Implementations", Proceedings of International Symposium on Microarchitecture, Workshop on Media and Stream Processors, Austin, TX, December 2, 2001
  • W. Stechele, "Algorithmic Complexity, Motion Estimation and a VLSI Architecture for MPEG-4 Core Profile Video Codecs", Proceedings of VLSI-TSA International Symposium on VLSI Technology, Systems and Applications, Taiwan, April 18-20, 2001
  • W. Stechele, "A VLSI Architecture for MPEG-4 Core Profile Video Codecs", Proceedings of DCIS2000 Design of Circuits and Integrated Systems Conference, Montpellier, November 21 - 24, 2000, pp. 440-443
  • W. Stechele, "Entwicklung von VLSI Architekturen für die Videosignalverarbeitung in Multimedia-Endgeräten", Habilitation Thesis accepted by the Department of Electrical Engineering and Information Technology, Munich University of Technology, July, 2000
  • S. Herrmann, H. Mooshofer, H. Dietrich, W. Stechele, "A Video Segmentation Algorithm for Hierarchical Object Representations and Its Implementation", IEEE Transactions on Circuits and Systems for Video Technology, Special Issue on Object-Based Video Coding and Description, Vol. 9, No. 8, December, 1999, pp. 1204-1215
  • H. Mooshofer, S. Herrmann, W. Stechele, "A Motion Analysis Method for a Hierarchical Segmentation Algorithm and its Efficient Implementation", WIAMIS `99, Berlin, June, 1999
  • S. Herrmann, R. Sasportas, H. Mooshofer, J.-C. Klein, F. Meyer, W. Stechele, "Application of recursive methods for the object based video processing and feature extraction", WIAMIS `99, Berlin, June, 1999
  • P. Kuhn, U. Niedermeier, L.-F. Chao, W. Stechele, "A flexible low-power VLSI architecture for MPEG-4 motion estimation", Vol. SPIE 3653, Visual Communications and Image Processing, San Jose, California, Januar, 1999
  • P. Kuhn, G. Diebel, S. Herrmann, A. Kaup, A. Keil, R. Mayer, H. Mooshofer, W. Stechele, "Complexity and PSNR-Comparison of several Fast Motion Estimation Algorithms for MPEG-4", vol. SPIE 3460 Applications of Digital Image Processing XXI, San Diego, July, 1998
  • P. Kuhn, W. Stechele, "Complexity Analysis of the Emerging MPEG-4 Standard as a Basis for VLSI Implementation", vol. SPIE 3309 Visual Communications and Image Processing, San Jose, January, 1998, pp. 498-509
  • S. Herrmann, H. Mooshofer W. Stechele, "An Architecture Concept for Hardware Accelerated Image Segmentation", DCIS `97, Sevilla, November, 1997
  • A. Hutter, C. Graber, P. Kindsmueller, W. Stechele, "A Flexible Hardware Accelerator for Filter Algorithms in Digital Video Coding", Conference on Design of Circuits and Integrated Systems, Sevilla, November, 1997
  • M. Zeller, W. Aicher, P. Kuhn., W. Stechele, "Hard- und Softwareaspekte der Videocodierung - Teil 2: Videoprozessoren und Architekturen", F&M, Zeitschrift fuer Elektronik, Optik und Mikrosystemtechnik, Nr. 10, 105 Jahrgang, Carl Hanser Verlag, Muenchen, October, 1997, pp. 698-702
  • P. Kuhn, M. Eiermann, W. Stechele, "A flexible Segment Matching Processor for Motion and Illumination Estimation", PCS 97, International Picture Coding Symposium, Berlin, September, 1997
  • P. Kuhn, A. Weisgerber, R. Poppenwimmer, W. Stechele, "Eine flexible Architektur für moderne Verfahren der Bewegungsschätzung", 7. Dortmunder Fernsehseminar, Dortmund, September, 1997
  • P. Kuhn, W. Stechele, "VLSI architecture for variable block size motion estimation with luminance correction", vol. SPIE 3162 Advanced Signal Processing: Algor, July, 1997, pp. 497-508
  • P. Kuhn, A. Weisgerber, R. Poppenwimmer, W. Stechele, "A flexible VLSI architecture for Variable Block Size Segment Matching with Luminance Correction", ASAP 97, IEEE International Conference on Application-specific Systems, Architectures and Processors, Zurich, July, 1997
  • P. Kuhn, M. Eiermann, W. Weisgerber, R. Poppenwimmer, W. Stechele, "VLSI Implementation of Mean-Corrected Block-Matching Motion Estimation of Partial Quadtrees", VLBV 97, Workshop for Very Low Bitrate Video Coding, Linkvping,Sweden, July, 1997
  • S. Herrmann, H. Mooshofer, W. Stechele, "A Toolbox Approach for Image Segmentation and Complexity Analysis", WIAMIS `97, Leuven-La-Neuve, June, 1997
  • M. Zeller, P. Kuhn, A. Hutter, W. Stechele, "Hard- und Softwareaspekte der Videocodierung - Teil 1: Prinzipien und Standards", F&M, Zeitschrift fuer Elektronik, Optik und Mikrosystemtechnik, Jahrgang, 105, Carl Hanser Verlag, Muenchen, May, 1997, pp. 338-342
  • P. Kindsmüller, M. Movahedin, W. Stechele, "A New Design Methodology Tolerant Against Design Errors", 1st IEEE International High Level Design Validation and Test Workshop, San Jose, USA, 1996
  • M. Movahedin, P. Kindsmüller, W. Stechele, "Modelling of VHDL Design Errors and Methods for their Correctability", International VHDL Users Forum (VIUF), Santa Clara, USA, February, 1996
  • H. Mooshofer, A. Hutter, W. Stechele, "Parallelization of a H.263 encoder for the MVP", DSP Education and Research Conference, Paris, September, 1996