Sie befinden sich hier: Mitarbeiter / 

Ordinarius
Theresienstr. 90, Gebäude N1, Raum N2121
herkersdorf@tum.de
Tel. 089 / 289-22515
Fax 089 / 289-28323


Biography

Andreas Herkersdorf is a Full Professor and Chair of the Integrated Systems Laboratory at Munich University of Technology. He teaches graduate courses in digital integrated circuit design, the application of System on Chip technology in networking and communications, and Hardware/Software-Codesign.

He joined the IBM Zurich Research Laboratory as a PhD student in 1988. In 1991, he became a Research Staff Member in the Communications Systems department of the IBM Zurich and in 2000 manager of the network processor hardware group.

Andreas Herkersdorf was born in 1961 in Oberstdorf, Germany. He received the Dipl.-Ing. degree from Munich University of Technology in 1987 and the Dr. techn. degree from the ETH Zurich (Swiss Federal Institute of Technology), Switzerland, in 1991, both in electrical engineering



Research Interests

Platform-based multi-processor System on Chip (MPSoC) architectures
Design and prototype development of innovative Hardware IP (Intellectual Property) building blocks
High-level SoC design space exploration and Autonomic Computing


Awards

2001: IBM Outstanding Technical Achievement Award
1998: IBM Master Inventor
Vier IBM Innovation Achievement Awards im Zeitraum zwischen 1996 und 2003




Publikationen

  • R. Ohlendorf, M. Meitinger, T. Wild, A. Herkersdorf, "An Application-aware Load Balancing Strategy for Network Processors", HiPEAC 2010 International Conference on High-Performance Embedded Architectures and Compilers, January 25-27, 2010
  • A. Lankes, A. Herkersdorf, S. Sonntag, H. Reinig, "NoC Topology Exploration for Mobile Multimedia Applications", The 16th IEEE International Conference on Electronics, Circuits and Systems, Medina, Tunesien, December 13-16, 2009
  • R. Ohlendorf, M. Meitinger, T. Wild, A. Herkersdorf, "FlexPath NP- Flexible, Dynamically Reconfigurable Processing Paths in Network Processors. In: Dynamically Reconfigurable Systems, Architectures, Design, Methods and Applications", Springer Verlag, December, 2009, ISBN: 978-90-481-348
  • A. Lankes, T. Wild, A. Herkersdorf, "Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources", Euromicro Conference on Digital System Design (DSD 2009), Patras, Greece, August 27-29, 2009
  • S. Traboulsi, M. Meitinger, R. Ohlendorf, A. Herkersdorf, "An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs", 12th Euromicro Conference on Digital System Design (DSD09), Patras, Greece, August 27-29, 2009
  • Z. Wang, A. Herkersdorf, "Flow Analysis on Intermediate Source Code for WCET Estimation of Compiler-Optimized Programs", The 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2009), Beijing, China, August 24-26, 2009
  • Z. Wang, W. Haberl, M. Wechs, A. Herkersdorf, "SysCOLA: A Framework for Co-Development of Automotive Software and System Platform", 46th Design Automation Conference (DAC 09), San Francisco, USA, July 26-31, 2009 (Download...)
  • Z. Wang, A. Herkersdorf, "An Efficient Approach for System-Level Timing Simulation of Compiler-Optimized Embedded Software", 46th Design Automation Conference (DAC 09), San Francisco, USA, July 26-31, 2009
  • Z. Wang, A. Herkersdorf, "Software performance simulation strategies for high-level embedded system design", International Journal of Performance Evaluation (Impact Factor: 1.524), July, 2009
  • C. Köhler, A. Mayer, A. Herkersdorf, "Chip Hardware-in-the-Loop Simulation (CHILS) Coupling Optimization through new Algorithm Analysis Technique", Proceedings 16th International Conference Mixed Design of Integrated Circuits and Systems, Lódź, Poland, June 25-27, 2009
  • D. Llorente, K. Karras, T. Wild, A. Herkersdorf, "Advanced Packet Segmentation and Buffering Algorithms in Network Processors", In: Transaction on High Performance Embedded Architectures and Compilers, 2009
  • M. Meitinger, R. Ohlendorf, T. Wild, A. Herkersdorf, "FlexPath NP - A Network Processor Architecture with Flexible Processing Paths", International Symposium on System-on-Chip (SoC 2008), Tampere, Finnland, November 4-6, 2008
  • Z. Wang, W. Haberl, A. Herkersdorf, M. Wechs, "A Simulation Approach for Performance Validation during Embedded Systems Design", 3rd International Symposium on Leveraging Applications of Formal Methods, Verification and Validation (ISoLA'08), Chalkidiki, Greece, October 13-15, 2008
  • R. Ohlendorf, M. Meitinger, T. Wild, A. Herkersdorf, "A Processing Path Dispatcher in Network Processor MPSoCs", IEEE Transactions on VLSI Systems, Vol. 16, Issue 10, October, 2008, pp 1335-1345
  • Z. Wang, S. Merenda, M. Tautschnig, A. Herkersdorf, "A Model Driven Development Approach for Implementing Reactive Systems in Hardware", International Forum on Specification and Design Languages (FDL'08), Stuttgart, Germany, September 23-25, 2008
  • J. Zeppenfeld, A. Bouajila, W. Stechele, A. Herkersdorf, "Learning Classifier Tables for Autonomic Systems on Chip", Lecture Notes in Informatics, Springer, Gesellschaft für Informatik, GI Jahrestagung, München, September 12, 2008, Vol. 134, p. 771-778
  • C. Köhler, A. Mayer, A. Herkersdorf, "Determining the Fidelity of Hardware-In-the-Loop Simulation Coupling Systems", Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Conference, San Jose, California, September 25-26, 2008, pp. 13-18
  • T. Pionteck, R. Koch, C. Albrecht, E. Maehle, M. Meitinger, R. Ohlendorf, T. Wild, A. Herkersdorf, "SPP1148 Booth: Network Processors", Field Programmable Logic and Applications (FPL08), Heidelberg, Germany, September 8-10, 2008
  • K. Karras, D. Llorente, T. Wild, A. Herkersdorf, "Improving Memory Subsystem Performance in Network Processors with Smart Packet Segmentation", SAMOS IC VIII, Samos, Griechenland, July 21-24, 2008
  • D. Llorente, K. Karras, T. Wild, A. Herkersdorf, "Buffer Allocation for Advanced Packet Segmentation in Network Processors", Application-specific Systems, Architectures and Processors 2008, Leuven, Belgium, July 2-4, 2008
  • Z. Wang, A. Sanchez, A. Herkersdorf, "SciSim: A Software Performance Estimation Framework using Source Code Instrumentation", ACM International Workshop on Software and Performance (WOSP'08), Princeton, NJ, USA, June 23-26, 2008
  • Z. Wang, A. Sanchez, A. Herkersdorf, W. Stechele, "Fast and Accurate Software Performance Estimation during High-Level Embedded System Design", edaworkshop, Hannover, Deutschland, May 6-7, 2008 (Download...)
  • C. Köhler, A. Mayer, A. Herkersdorf, "Chip Hardware In-The-Loop Simulation (CHILS) – Embedding Microcontroller Hardware In Simulation", IASTED Modelling and Simulation Conference 2008, Quebec City/Canada, May 26-28, 2008
  • A. Herkersdorf, J. Zeppenfeld, A. Bouajila, W. Stechele, "Hardware-Supported Learning Classifier Tables in Autonomic Systems on Chip", Dagstuhl Seminar 08141, March 30 - April 4, 2008
  • M. Ihmig, N. Alt, C. Claus, A. Herkersdorf, "Resource-efficient Sequential Architecture for FPGA-based DAB Receiver", Workshop zu Software Radio “WSR 08”, Karlsruhe, March 5-6, 2008 (Download...)
  • M. Meitinger, R. Ohlendorf, T. Wild, A. Herkersdorf, "A Hardware Packet Resequencer Unit for Network Processors", International Conference on Architecture of Computing Systems (ARCS 2008), Dresden, February 25-28, 2008
  • R. Ohlendorf, M. Meitinger, T. Wild, A. Herkersdorf, "A Packet Classification Technique for On-Chip Processing Path Selection", Proceedings of the 5th Workshop on Application Specific Processors (WASP'07), pp. 95-102; Salzburg, October 4-5, 2007 (Download...)
  • R. Ohlendorf, T. Wild, M. Meitinger, H. Rauchfuss, A. Herkersdorf, "Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications", Journal of Systems Architecture; http://dx.doi.org/10.1016/j.sysarc.2007.01.009; Vol. 53, No. 10, October, 2007, pp 703-718
  • C. Claus, W. Stechele, A. Herkersdorf, "Autovision-A Run-time Reconfigurable MPSoC Architecture for future Driver Assistance Systems", it - Information Technology Journal, Issue No. 3, June 20, 2007 (Download...) (ext. Link...)
  • W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld, D. Ziener, "Concepts for Autonomic Integrated Systems", eda-Workshop, Hannover, June 19-20, 2007
  • M. Meitinger, R. Ohlendorf, T. Wild, A. Herkersdorf, "A Programmable Stream Processing Engine for Packet Manipulation in Network Processors", IEEE Computer Society Annual Symposium on VLSI, 2007 (ISVLSI '07), Porto Alegre, Brazil, May 9-11, 2007
  • A. Herkersdorf, W. Stechele, "Exploitation of Reconfiguration in Advanced Applications Run-Time Reconfiguration for High Performance Video-based Driver Assistance and High-Speed IP Networking", DATE 2007 Tutorial on Reconfigurable Computing: Architectures, Tools and Applications, Nice, France, April, 16-20, 2007
  • W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld, D. Ziener, "Autonomic MPSoCs for Reliable Systems", GMM/GI/ITG Fachtagung Zuverlässigkeit und Entwurf, ZuD, March 27-28, Munich, Germany, 2007
  • D. Llorente, K. Karras, M. Meitinger, H. Rauchfuss, T. Wild, A. Herkersdorf , "Accelerating Packet Buffering and Administration in Network Processors", International Symposium on Intergrated Circuits 2007, 2007 (Download...)
  • T. Wild, A. Herkersdorf, G.-Y. Lee, "TAPES - Trace-based architecture performance evaluation with SystemC, Design Automation for Embedded Systems", Vol. 10, Numbers 2-3, Special Issue on SystemC-based System Modeling, Verification and Synthesis, 2006, pp 157-179 (ext. Link...)
  • A. Herkersdorf, C. Claus, M. Meitinger, R. Ohlendorf, T. Wild, "Reconfigurable Processing Units vs. Reconfigurable Interconnects", Dagstuhl Seminar on Dynamically Reconfigurable Architectures, Dagstuhl Seminar Proceedings 06141, April 2-7, 2006 (ext. Link...)
  • T. Wild, A. Herkersdorf, R. Ohlendorf, "Performance Evaluation for System-on-Chip Architectures using Trace-based Transaction Level Simulation", Design Automation & Test in Europe (DATE), March 6-10, 2006
  • R. Ohlendorf, T. Wild, M. Meitinger, H. Rauchfuss, A. Herkersdorf, "Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications", Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006
  • A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, A. Bernauer, O. Bringmann, W. Rosenstiel, "Organic Computing at the System on Chip Level", Proceedings of the IFIP International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2006). Springer, October, 2006
  • A. Bernauer, O. Bringmann, W. Rosenstiel, A. Bouajila, W. Stechele, A. Herkersdorf, "An Architecture for Runtime Evaluation of SoC Reliability", INFORMATIK 2006 - Informatik für Menschen, volume P-93 of GI-Edition - Lecture Notes in Informatics, Bonn, Köllen Verlag. to be published, September, 2006, pp. 177-185
  • A. Bouajila, A. Bernauer, A. Herkersdorf, W. Rosenstiel, O. Bringmann, W. Stechele, "Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoC", Yi Pan, Franz J. Rammig, Hartmut Schmeck, and Mauricio Solar, editors, 1st IFIP International Conf., on Biologically Inspired Cooperative Computing (BICC 2006), vol. 216, Springer, Boston, August, 2006, pp. 107-113
  • R. Ohlendorf, A. Herkersdorf, T. Wild, "FlexPath NP - A Network Processor Concept with Application-Driven Flexible Processing Paths", CODES+ISSS'2005, Jersey City, NJ, USA, September 19-21, 2005 (Download...)
  • D.E. Taylor, A. Herkersdorf, A. Döring, G. Dittmann, "Robust Header Compression (ROHC) in Next-Generation Network Processors", IEEE/ACM Transactions on Networking, Vol. 13, Issue 4, Aug., 2005, pp 755-768
  • G. Lipsa, A. Herkersdorf, W. Rosenstiel, O. Bringmann, W. Stechele, "Towards a Framework and a Design Methodology for Autonomic SoC", International Conference on Autonomic Computing, ICAC-05, Seattle, June 13-16, 2005
  • P. Zuber, A. Windschiegl, R. Medina, W. Stechele, A. Herkersdorf, "Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization", Design, Automation & Test in Europe, DATE-05, Munich, March, 2005
  • A. Herkersdorf, W. Rosenstiel, "Towards a Framework and a Design Methodology for Autonomic Integrated Systems", Workshop Organic Computing, GI Jahrestagung, Ulm, pp. 610-615, September, 2004
  • C. Albrecht, R. Hagenau, E. Maehle, A. döring, A. Herkersdorf, "A Comparison of Parallel Programming Models of Network Processors", PASA 04, 7th Workshop Parallel Systems and Algorithms, Lecture Notes in Informatics (LNI), Augsburg, Germany, 2004, pp 390-399
  • C. Albrecht, R. Hagenau, E. Maehle, A. Döring, A. Herkersdorf, "A Comparison of Parallel Programming Models of Network Processors ", PASA 2004, 7th Workshop 'Parallel Systems and Algorithms' in connection with ARCS 2004, 17th Int. Conf. on Architecture of Computing Systems - Organic & Pervasive Computing - Augsburg, March 23 - 26, 2004
  • W. Stechele, S. Herrmann, A. Herkersdorf, "Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing", International Conference on Architecture of Computing Systems, ARCS 2004, Augsburg, Germany, March 23-26, 2004