Lehrveranstaltungen

Betreuer für die Übungen Digital IC Design und ISNC

Publikationen

M. May, N. Wehn, A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, D. Ziener, J. Teich, "A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip", DATE Conference 2010, Dresden, March 8-12, 2010
A. Bouajila, J. Zeppenfeld, A. Herkersdorf, W. Stechele, "Multi-Bit Error Protection", edaWorkshop, Dresden, May 26-28, 2009
A. Bouajila, T. Sommer, J. Zeppenfeld, W. Stechele, A. Herkersdorf, "A Fault-Tolerant Processor Architecture", ARCS 2009, Workshop „Dependability and Fault-Tolerance, Delft, March 10-13, 2009
J. Zeppenfeld, A. Bouajila, W. Stechele, A. Herkersdorf, "Learning Classifier Tables for Autonomic Systems on Chip", Lecture Notes in Informatics, Springer, Gesellschaft für Informatik, GI Jahrestagung, München, September 12, 2008, Vol. 134, p. 771-778
A. Herkersdorf, J. Zeppenfeld, A. Bouajila, W. Stechele, "Hardware-Supported Learning Classifier Tables in Autonomic Systems on Chip", Dagstuhl Seminar 08141, March 30 - April 4, 2008
A. Lankes, T. Wild, J. Zeppenfeld, "System Level Simulation of Autonomic SoCs with TAPES", ARCS 2008 - Architecture of Computing Systems, Dresden, February 25-28, 2008
A. Lankes, T. Wild, J. Zeppenfeld, "Power Estimation of Time Variant SoCs with TAPES", 10th EUROMICRO Conference on Digital System Design: Architectures, Methods, Tools (DSD 07), August 29-31, 2007
W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld, D. Ziener, "Concepts for Autonomic Integrated Systems", eda-Workshop, Hannover, June 19-20, 2007
C. Claus, J. Zeppenfeld, W. Stechele, "Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance Systems", Proceedings of DATE 2007, Nice, France, April 16-20, 2007 (ext. Link...)
W. Stechele, O. Bringmann, R. Ernst, A. Herkersdorf, K. Hojenski, P. Janacik, F. Rammig, J. Teich, N. Wehn, J. Zeppenfeld, D. Ziener, "Autonomic MPSoCs for Reliable Systems", GMM/GI/ITG Fachtagung Zuverlässigkeit und Entwurf, ZuD, March 27-28, Munich, Germany, 2007
C. Claus, J. Zeppenfeld, F. H. Müller, W. Stechele, "A new framework to accelerate VirtexII Pro dynamic partial self-reconguration", 14th Reconfigurable Architectures Workshop, Long Beach, CA, March 26-27, 2007 (ext. Link...)
A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, A. Bernauer, O. Bringmann, W. Rosenstiel, "Organic Computing at the System on Chip Level", Proceedings of the IFIP International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2006). Springer, October, 2006