Seminar on Topics in Integrated System Design (Seminar)
|Lecturer (assistant/s)||Ulf Schlichtmann, Andreas Herkersdorf (Helmut Gräb, Christian Herber, Daniel Müller-Gritschneder)|
|Allocation to curriculum||See TUMonline|
|Offered in||Wintersemester 2016/17|
|Semester weekly hours||3|
|Scheduled dates||See TUMonline|
Students have to choose a seminar topic before the introduction lesson. You need to contact a supervisor of a topic you are interested in. Topics are selected on a first come first served basis. You are only registered for the seminar after your topic supervisor has confirmed your chosen topic. For a list of topics refer to the following links: This seminar is jointly organized by Prof. Schlichtmann (http://www.eda.ei.tum.de/lehrveranstaltungen/seminare/integrated-system-design/) and Prof. Herkersdorf (http://www.lis.ei.tum.de/?id=stisd).
Topics are made available online on Oct. 5th, 2015.
Objective (expected results of study and acquired competences)
* self dependent learning of a scientific topic
* improving your oral presentation skills
* writing a scientific report
* designing a scientific paper
**The greatest ideas are worthless if you keep them to yourself**
The careful development of new results and methods is not enough to inspire your listeners, colleagues, or boss in your work. No less important is an understandable and convincing presentation of your achievements. The goal of the seminar is to improve these presentation skills.
Specific seminar topics in the area of electronic design automation and electronic systems architecture will be offered. Examples are analog design methodology, digital design methodology, layout synthesis, system-level design methodology, application-specific accelerators and function-specific processor architecture.
The participants independently work on a scientific topic, write a paper of 2-4 pages and a poster, and present their topic in a talk. In the subsequent discussion the topic will be treated in-depth.
Teaching and learning method (delivery of skills)
Students elaborate a given scientific topic by themselves in coordination with the respective research assistant.
One introductory lesson is given by the course coordinator, further details are discussed between research assistant and student on an individual basis.
All current techniques for preparing and presenting papers and talks will be applied, e.g.
- blackboard, whiteboard
- electronic slides, beamer
- electronic word processing
- electronic slide processing
Assessment (exam method and evaluation)
* Written contribution consisting of paper and poster (50%)
* 20-minutes presentation followed by 5 minutes discussion (50%)
|Crosstalk in on-Chip Interconnect||Feature size reduction is still one of the drivers to keep Moore's Law alive. For the interconnect in a System-on-Chip, this means that also the distances between the signal wires become smaller, and the shielding against adjacent wires decreases. Consequently, wires are not independent of their surrounding neighbors anymore, and thus a phenomenon called crosstalk arises, where the state of a wire is changed due to the state of an adjacent one. In this seminar, the problem of crosstalk on modern SoC designs shall be highlighted, by giving an overview of state-of-the art crosstalk models and by providing typical values of crosstalk induced bit errors.||Vonbun|
|Optical on-Chip Interconnects||To enable high data rate and low latency demands, optical fibre and optical data transmission are well known and widely deployed not only in the internet backbone but are also pushing to the end user by offering fibre-to-the-home or fibre-to-the-building in certain urban areas. On-Chip interconnects, however, are mostly dominated by conventional electrical transmission schemes, as they integrate well in the CMOS processes, are compatible with conventional buffers, and allow for a wide variety of different interconnects, ranging from shared buses to both circuit and packet switched Networks-on-Chips. In this seminar, the state-of-the-art of optical on-Chip communication shall be reviewed, discussing promises, challenges, advantages and disadvantages of a novel and emerging interconnect technology.||Vonbun|
|Memristor & Carbon Nanotube Transistor||While reaching and exploring the post-CMOS and beyond von Neumann era, new mechanisms of logic design and in-memory computing will attract more and more attention, giving rise to an ever growing number of different computing approaches. The goal of this seminar is to explore both the potential and limitation of two completely different approaches, i.e. memristor and carbon nanotube transistor. Such approaches may depend either purely on the properties of single devices, or on the collective behavior of many interconnected devices. An overview should be given on related state-of-the-art from device level up to logic and system level. The topic might be shared by a team of two students, with a focus on memristor and CNT, respectively.||Stechele|
|Cache Coherence and Data/Task Placement||Today, almost every electronic device (e.g. Smartphones, Laptops, etc.) is based on a multi-core environment. This brings a lot of advantages and speedup, but at the cost of some others issues, like mainting correctness in the communication and interaction of several cores, especially if they operate on shared data. This is called cache/memory coherence. Since multi-core platforms need a Network-on-Chip (NoC) to be scalable, the cores and also the memory is or can be distributed. This poses some challenges for Cache Coherence. The goal of this seminar is to study the influence of Data/Task Placement on the performance and efficiency of cache coherence.||Rheindt|
|Dynamic Thermal Management for Manycore Systems||Todays high performance chip multicore processors are mostly temperature limited. Increasing the operating frequency or the percentage of active silicon would lead to burning chips. Therefore, effective dynamic thermal management (DTM) is an important research challenge for academia and industry alike. In this seminar, you will survey state-of-the-art DTM literature and classify proposed solutions. Furthermore, you should lay a focus on future manycore systems with 100+ cores and associated DTM challenges.||Sagi|
|Energy Inefficiencies due to Application Interference||Firefox, steam, skype, the operating system and a multitude of other tasks usually run in parallel on todays chip multicore processors.To make optimal power management (DVFS and DPM) and scheduling decisions we would like to know how each task behaves, e.g. execution time, memory hungriness. Many solutions have been proposed for the (seldom encountered) case of each application running isolated from the others. However, multiple applications running in parallel and interfering with each other, i.e. accessing shared resources, is far more realistic. In this seminar you will survey existing literature on application interference on multicore systems with a special focus on energy inefficiencies.||Sagi|
|Efficient Invalidation Techniques for Cache Coherence on a NoC-based Multi-Core Platform||Today, almost every electronic device (e.g. Smartphones, Laptops, etc.) is based on a multi-core environment. This brings a lot of advantages and speedup, but at the cost of some others issues, like mainting correctness in the communication and interaction of several cores, especially if they operate on shared data. This is called cache/memory coherence. Since multi-core platforms need a Network-on-Chip (NoC) to be scalable, the cores and also the memory is or can be distributed. This poses some challenges for Cache Coherence. The goal of this seminar is to study and compare Efficient Invalidation Techniques for cache coherence on a NoC-based multi-core platform.||Rheindt|
|NoC-Level Support for Mixed-Criticality||Modern cars typically contain up to 100 different Electronic Control Units (ECUs) that are used to implement different functions, such as driver assistance or infotainment systems. To reduce this number, a lot of these functions can be consolidated onto a few MPSoCs, which usually use a Network-on-Chip (NoC) for communication. This creates the problem that applications of different criticality share and compete for the same resources (especially the NoC) and thereby affect one another. The goal of this seminar is to survey different approaches to support mixed-criticality on NoC-level, to prevent low-priority applications from negatively affecting the execution of safety critical applications.||Koenen|
|Fault-Aware NoC Routing||Some safety-critical applications, e.g. for autonomous driving, must be implemented as a fail-operational system that can continue its work even when parts of the hardware fail. When implementing such a fail-operational system on a Network-on-Chip (NoC)-based MPSoC, the system must be robust enough to tolerate parts of the NoC failing. The goal of this seminar is to survey different approaches to fault-aware routing in a NoC.||Koenen|
|Digital Hardware Verification Techniques||In the development of digital hardware, the goal is to have a "first time right" tapeout of a chip. To give chip developers the necessary confidence that this goal can be achieved, a lot of testing and verification is applied before a chip design is ready to be fabricated. The goal of this work is list and contrast several verification approaches used in industry and proposed in academia. A special focus should be on the agility of the method, i.e. how it enables to iterate quickly on a design problem by trying out different solution approaches.||Wagner|
|Hardware vs Software Coherence Schemes||In today's multi-core environment, cache/memory coherence plays a very important role in maintaining correctness of a given application. Primitively speaking, coherence support can be provided by means of hardware, software or a mixture of both. The goal of this seminar is to study and compare the different types of hardware and/or software coherence schemes for multi-core architectures.||Akshay|
|Snoop Filters: An Efficient Approach to Cache Coherence||In today's multi-core environment, cache/memory coherence plays a very important role in maintaining correctness of a given application. Based on the underlying interconnect architecture, coherence schemes can be broadly classified either as Snoop or Directory based schemes. This seminar topic focuses on snoop based coherence schemes and how they can be made more efficient by eliminating unwanted snoops. The goal of this seminar is to study and compare different snoop filtering schemes for multi-core architectures.||Akshay|
|Fault tolerant network interface design for NoCs||NoCs constitute the interconnection architecture of the future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. But as the complexity of designs increases and technology scales down into the deep submicron domain, the probability of malfunctions and failures in the NoCs components increases. This topic studies the network interface hardware of NoC, the failures that can happen in this component and possible solutions and designs for fault tolerant network interfaces.||Sadighi|
|Fault tolerant router design for NoCs||NoCs constitute the interconnection architecture of the future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. But as the complexity of designs increases and technology scales down into the deep sub-micron domain, the probability of malfunctions and failures in the NoCs components increases. This topic studies the router hardware of the NoC, the failures that can happen in this component and possible solutions and designs for fault tolerant routers in NoCs.||Sadighi|
|Network Load Balancing||Network data rates continue to grow rapidly. In order to satisfy Quality-of-Service demands, to decrease cost and to increase reliability, network loads are commonly distributed across multiple network links and network processing devices (e.g. switches, firewalls, intrusion-detection systems etc.). The goal of this seminar topic is to survey different load balancing approaches, with a specific focus on their hardware implementation.||Oeldemann|
|Statical WCET-Analysis for Multi-Core Systems||It is indispensable to know the worst-case execution time (WCET) for the development of real-time systems. There exist several methods to approximate the WCET on single-core platforms. Whenever multiple tasks run simultaneously on a multi-core platform, these methods cannot provide a reliable estimation any more. The goal of this seminar is to summarize the major problems which arise when analysing multi-core applications and some methods to solve them.||Gabriel|