Srivatsa Akshay, M.Sc.

Wissenschaftlicher Mitarbeiter  

Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München

Tel.: +49.89.289.22963
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2140
Email: srivatsa.akshay@tum.de

Teaching

System-on-Chip Platforms (Since SS 2016)

BAMAIDPFPIPHSSHK
Titel

Vergebene Arbeiten

Masterarbeiten

Optimizing Region Based Cache Coherence for the InvasIC Architecture (HW)

Optimizing Region Based Cache Coherence for the InvasIC Architecture (HW)

Stichworte:
Cache Coherence, Distributed Directories, FPGA

Beschreibung

Providing hardware coherence for modern tile-based MPSoCs requires additional area. As a result, this does not scale with increasing tile counts. As part of the Invasive Computing project, we introduced Region Based Cache Coherence (RBCC) which is a dynamic scalable approach that provides on-demand coherence based on application requirements. However, the directories currently used for RBCC are not optimized for area. Therefore, RBCC can be further enhanced by optimizing these structures in conjunction with the coherency protocol for hybrid distributed shared memory MPSoCs.

Goal

The goal of this project is to optimize directory structures with smart replacement policiesand implement amodified coherence protocol to save on-chip area without sacrificing performance.

Towards this goal you’ll complete the following tasks:

  • Investigate existing directory based cache coherence schemes
  • Implement a smart directory stucture to reduce hardware overheads
  • Implement a hybrid cache coherence protocol for distributed shared memory systems
  • Verify the design on a FPFA-based hardware platform

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences:

  • Very Good VHDL Skills
  • Good C/C++ Skills
  • Good understanding of MPSoCs and Cache Coherence Schemes
  • Self-motivated and structured work style

Learning Objectives

 After you have successfully completed this project, you will be able to

  • Understand the challenges of cache coherence in multi-core systems
  • Understand the work flow from software-to-hardware

Kontakt

Akshay Srivatsa
Room N2140
Tel. 089 289 22963
srivatsa.akshay@tum.de

Betreuer:

Srivatsa Akshay Sateesh

Supervised Work

  • Accelerated Cache Coherence for the InvasIC Architecture
    (Research Internship, Yifang Wang, 2016)
  • High Level Modelling of the InvasIC Architecture using Gem5
    (Working Student, Mengyu Liang, 2016)

Publikationen

  • Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild and Andreas Herkersdorf: CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. ARCS 2018 - 31st International Conference on Architecture of Computing Systems, 2018 mehr… BibTeX
  • Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf: Region Based Cache Coherence for Tiled MPSoCs. 2017 30th IEEE International System-on-Chip Conference (SOCC), 2017 mehr… BibTeX