Akshay Srivatsa, M.Sc.

Wissenschaftlicher Mitarbeiter  

Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München

Tel.: +49.89.289.22963
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2140
Email: srivatsa.akshay@tum.de

Lehre

Project Laboratory IC Design (WS 2018-19)

System-on-Chip Platforms (Since SS 2016)

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Info:

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Titel
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Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype

Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype

Stichworte:
Cache Coherence, Distributed Shared Memory MPSoCs

Kurzbeschreibung:
The goal of this project is to extend RBCC to global memory with distributed directories.

Beschreibung

Providing hardware coherence formoderntile-based MPSoCsrequires additional area. As a result, this does not scale with increasing tile counts.As part of the Invasive Computing project, we introducedRegion Based Cache Coherence (RBCC) whichis ascalableapproachthat provides on-demand coherence. RBCC enables users to dynamically create/destroy coherency regions based on application requirements. Currently, RBCC has been developed for the distributed tile local memories of our system. The next step is to extend RBCC to the global memory, so as to fully utilize the memory capacity of our heterogeneous muticore architecture.

Towards this goal you’ll complete the following tasks:

  • Investigate existing distributed directory based cache coherence schemes

  • Extend RBCC to global DDR memory

  • Verify the design on a FPGA-based hardware platform

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences.

  • Very Good VHDL Skills

  • Good C/C++ Skills

  • Good understanding of MPSoCs and Cache Coherence Schemes

  • Self-motivated and structured work style

 

 

Kontakt

Akshay Srivatsa
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 22963
srivatsa.akshay@tum.de
www.lis.ei.tum.de

Betreuer:

Laufende Arbeiten

Masterarbeiten

Exploring the Dynamicity of Region Based Cache Coherence for Distributed Shared Memory MPSoCs on an FPGA Prototype

Exploring the Dynamicity of Region Based Cache Coherence for Distributed Shared Memory MPSoCs on an FPGA Prototype

Stichworte:
Cache Coherence, Distributed Shared Memory MPSoCs

Kurzbeschreibung:
The goal of this project is to explore the dynamicity of RBCC and minimize the context switching penalties.

Beschreibung

Providing hardware coherence for modern tile-based MPSoCs requires additional area. As a result, this does not scale with increasing tile counts. As part of the Invasive Computing project, we introduced Region Based Cache Coherence (RBCC) which is a scalable approach that provides on-demand coherence. RBCC enables users to dynamically create/destroy coherency regions based on application requirements. With such dynamicity, the associated context switching overheads like cache flushing, directory flushing, coherency region reconfigurations, etc. need to be investigated and optimized.

Towards this goal you’ll complete the following tasks:
• Investigate existing directory based cache coherence schemes
• Implement/Modify a dynamic framework for RBCC
• Verify the design on a FPGA-based hardware platform

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences:
• Very Good VHDL Skills
• Good C/C++ Skills
• Good understanding of MPSoCs and Cache Coherence Schemes
• Self-motivated and structured work style

Kontakt

Akshay Srivatsa
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 22963
srivatsa.akshay@tum.de
www.lis.ei.tum.de

Betreuer:

Forschungspraxis oder MSCE Forschungspraxis

False-Sharing Resolution: A Hardware Mechanism to Detect & Resolve False-Sharing for Region Based Cache Coherence

False-Sharing Resolution: A Hardware Mechanism to Detect & Resolve False-Sharing for Region Based Cache Coherence

Stichworte:
Cache Coherence, Distributed Shared Memory MPSoCs

Kurzbeschreibung:
The goal of this project is to detect & resolve false-sharing of cache lines in a Distributed Shared Memory MPSoC

Beschreibung

Providing hardware coherence for modern tile-based MPSoCs requires additional area. As a result, this does not
scale with increasing tile counts. As part of the Invasive Computing project, we introduced Region Based Cache
Coherence (RBCC) which is a scalable approach that provides on-demand coherence. RBCC enables users to
dynamically create/destroy coherency regions based on application requirements. RBCC is transparently enabled
using a highly modular Coherency Region Manager (CRM) module attached on the bus. The non-intrusiveness of
the CRM combined with NUMA properties can result in false-sharing of cache blocks. False-sharing not only
degrades performance but can also corrupt data. False-sharing can be easily alleviated by software alignment at
the cost of memory, therefore a hardware solution is preferred.

Towards this goal you’ll complete the following tasks:
• Investigate existing directory based cache coherence schemes
• Investigate the false-sharing problem and its possible solutions
• Implement a hardware mechanism to resolve false-sharing for RBCC
• Verify the design on a FPGA-based hardware platform

Voraussetzungen

To successfully complete this project, you should already have the following skills and
experiences.
• Very Good VHDL Skills
• Good C/C++ Skills
• Good understanding of MPSoCs and Cache Coherence Schemes
• Self-motivated and structured work style

Kontakt

Akshay Srivatsa
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 22963
srivatsa.akshay@tum.de
www.lis.ei.tum.de

Betreuer:

Betreute Arbeiten

  • Compact Directories with Hybrid Architecture Aware Eviction Policies for Distributed Shared Memory MPSoCs (Nael Fasfous, 2018)
  • Optimizing Cache Coherence for MPSoCs with Distributed Shared Memories using a High Level Simulation Model (Yifang Wang, 2018)
  • Accelerated Cache Coherence for the InvasIC Architecture
    (Research Internship, Yifang Wang, 2016)
  • High Level Modelling of the InvasIC Architecture using Gem5
    (Working Student, Mengyu Liang, 2016)

Publikationen

  • Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild and Andreas Herkersdorf: CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. ARCS 2018 - 31st International Conference on Architecture of Computing Systems, 2018 mehr… BibTeX
  • Leonard Masing, Akshay Srivatsa, Fabian Kress, Nidhi Anantharajaiah, Andreas Herkersdorf, Juergen Becker: In-NoC-circuits for low-latency cache coherence in distributed shared-memory architectures. 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018 mehr… BibTeX
  • Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf: Region Based Cache Coherence for Tiled MPSoCs. 2017 30th IEEE International System-on-Chip Conference (SOCC), 2017 mehr… BibTeX