Srivatsa Akshay, M.Sc.

Wissenschaftlicher Mitarbeiter  

Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München

Tel.: +49.89.289.22963
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2140
Email: srivatsa.akshay@tum.de

Lehre

Angebotene Arbeiten

BAMAIDPFPIPHSSHK
Title

Laufende Arbeiten

Betreute Arbeiten

  • Compact Directories with Hybrid Architecture Aware Eviction Policies for Distributed Shared Memory MPSoCs (Nael Fasfous, 2018)
  • Optimizing Cache Coherence for MPSoCs with Distributed Shared Memories using a High Level Simulation Model (Yifang Wang, 2018)
  • Accelerated Cache Coherence for the InvasIC Architecture
    (Research Internship, Yifang Wang, 2016)
  • High Level Modelling of the InvasIC Architecture using Gem5
    (Working Student, Mengyu Liang, 2016)

Publikationen

  • Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild and Andreas Herkersdorf: CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. ARCS 2018 - 31st International Conference on Architecture of Computing Systems, 2018 more… BibTeX
  • Leonard Masing, Akshay Srivatsa, Fabian Kress, Nidhi Anantharajaiah, Andreas Herkersdorf, Juergen Becker: In-NoC-circuits for low-latency cache coherence in distributed shared-memory architectures. 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018 more… BibTeX
  • Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf: Region Based Cache Coherence for Tiled MPSoCs. 2017 30th IEEE International System-on-Chip Conference (SOCC), 2017 more… BibTeX