Franz Biersack, M.Sc.

Wissenschaftlicher Mitarbeiter

Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München

Tel.: +49.89.289.23869
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2138
Email: franz.biersack@tum.de

Lebenslauf

  • Seit Nov. 2018, Doktorand am LIS
  • 2018, M.Sc., Elektro- und Informationstechnik, Technische Universität München
    Master Thesis: "Implementation of an Image Processing Algorithm" bei Airbus Defence and Space
  • 2016, B.Eng., Elektro- und Informationstechnik, Ostbayerische Technische Hochschule Regensburg
    Bachelor Thesis: "Entwicklung des Hardwarekonzepts eines Display Timing Analyzers" bei Continental Engineering Services
    Praktikant und Werkstudent während des Studiums bei Continental Engineering Services
  • 2012, Praktikant bei PCO

Angebotene Arbeiten

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Titel
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Hardware Acceleration Techniques for Virtualized Network Functions

Hardware Acceleration Techniques for Virtualized Network Functions

Beschreibung

Network traffic is known to traverse a number of different links before reaching its destination. In one way or another it is processed at each node of the network. These processing tasks range from simple IP forwarding to more complex operations like the deployment of firewalls. Network functions traditionally were realized using dedicated proprietary hardware which is now more and more replaced by commodity servers executing the same tasks in software, effectively virtualizing the network functions. Since general purpose computing equipment however is inherently slower in direct comparison, recent approaches to improve their performance attempt to support them using hardware accelerators like FPGAs, ASICs or NPUs.

 

The goal of this seminar topic is to investigate state of the art hardware acceleration techniques to improve virtualized network function performance.

Betreuer:

Franz Biersack
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Demand aware Power Management in modern Multi-Core Processors

Demand aware Power Management in modern Multi-Core Processors

Beschreibung

For decades microprocessors have been operated at higher and higher clock frequencies to steadily raise their processing power. Hitting the power wall in the early 2000s however, a paradigm shift of performance increases by simply increasing the frequency set in. Instead, higher numbers of processor cores were used to achieve further performance advantages. And while modern processors still allow for clock frequencies of several GHz their workload often varies significantly and operating them with a lower clock frequency is easily sufficient. This also allows for lower supply voltages which overall can considerably save power consumption. Thus, modern CPUs provide interfaces designed to control the operating frequency and voltage they are supplied with, to save energy and extend their life cycle.

 

The goal of this seminar topic is to investigate mechanisms, advantages and drawbacks of state of the art power and thermal management technologies in modern multi-core processors.

Betreuer:

Franz Biersack

Publikationen

  • Gerard Vives Vallduriola, Tim Helfers, Franz Biersack, Steffen Linssen, Dr. Jens Utzmann, Alessandro Vananti: THE USE OF DIFFERENT ARCHITECTURES AND STREAK OBSERVATIONS ALGORITHMS TO DETECT SPACE DEBRIS. 6th International Workshop on On-Board Payload Data Compression, 2018 mehr… BibTeX