Max Koenen, M.Sc.

Wissenschaftlicher Mitarbeiter  

Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München

Tel.: +49.89.289.23084
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2118
Email: max.koenen@tum.de

Lehre

SystemC Laboratory (seit WS 2016/17)

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Design and Implementation of a Network Interface for a Fault-Tolerant Time-Division Multiplexed Network on Chip

Design and Implementation of a Network Interface for a Fault-Tolerant Time-Division Multiplexed Network on Chip

Description

Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
In order to implement a safety-critical real-time application on such an MPSoC, the NoC must fulfill certain requirements: it must ensure that no critical data gets lost, all critical data gets delivered within a certain deadline, and other applications cannot interfere with the critical application. And all this must be guaranteed even in case of a fault in the NoC.

Goal

The goal of this thesis is to implement a Network Interface for a Time-Division Multiplexed NoC that meets the criteria described above and create tests to validate the behavior of the implemented hardware.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences:

  • Very good programming skills in a hardware description language i.e. VHDL or (System)Verilog
  • Solid Python programming skills
  • At least basic knowledge of the functionality of NoCs
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • understand the concept of TDM NoCs
  • design and implement a complex hardware module in SystemVerilog
  • create tests to validate hardware modules
  • document your work in form of a scientific report and a presentation

 

 

Contact

Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de

Supervisor:

 

Unter Umständen sind auch Arbeiten möglich, die hier nicht explizit ausgeschrieben sind und sich grob in meinem Forschungsgebiet bewegen. Gerne kannst du mit einer Themenidee vorbeikommen, häufig finden wir dann eine Lösung!

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Bachelor's Theses

Implementation and Evaluation of a UART Controller

Implementation and Evaluation of a UART Controller

Description

To interact with an embedded system UART is still the dominant method. To reduce the number of I/O pins, tunneling UART over the existing debug interface is beneficial.

Goal

The goal of this thesis is to develop a well-known UART controller (16550) in hardware as part of the Open SoC Debug project.
Towards this goal you’ll complete the following tasks:

  • Learn about the standard UART 16550 chip and its interfaces.

  • Implement the interfaces in hardware running on an FPGA.

  • Implement a virtual tty interface as part of the Open Soc Debug software implementation.

  • Document your work in a written report and present your work in a presentation.

 

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Experience in a HDL language (VHDL or Verilog)
  • Ideally experience with hardware design and I/O interfaces.

  • Self-motivated and structured work style

Supervisor:

Master's Theses

Design and Implementation of a Fault-Tolerant Low-Throughput Broadcast Control & Management Network for System on Chip

Design and Implementation of a Fault-Tolerant Low-Throughput Broadcast Control & Management Network for System on Chip

Description

Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
One way of organizing the access to such a NoC is by using Time-Division Multiplexing (TDM) which
allows to give service guarantees. However, such a TDM NoC must be configured before it can be used which requires a reliable configuration network.

Goal

The goal of this thesis is to implement a reliable broadcast configuration network that can be used to configure the routers and network interfaces of a TDM NoC and to create tests to validate the implemented hardware.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences:

  • Good programming skills in a hardware description language i.e. VHDL or (System)Verilog
  • Good knowledge of on-chip communication
  • Solid Python programming skills
  • At least basic knowledge of the functionality of NoCs
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • understand the concept of TDM NoCs
  • create and extend hardware modules in SystemVerilog
  • create tests to validate hardware modules
  • document your work in form of a scientific report and a presentation

 

Contact

Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de

Supervisor:

Forschungspraxis or MSCE Internships

Implementation of Fault-Injection & Fault-Detection Mechanisms in a Time-Division Multiplexed Network on Chip

Implementation of Fault-Injection & Fault-Detection Mechanisms in a Time-Division Multiplexed Network on Chip

Description

Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
To implement safety-critical real-time applications on such an MPSoC, the NoC must be fault-tolerant. In order to fulfill this requirement, it is necessary to first detect a fault in the system. Furthermore, to test this requirement, it is necessary to be able to inject errors into the system at random times and places.

Goal

The goal of this thesis is to implement a fault-injection and a fault-detection mechanism in a Time-Division Multiplexed (TDM) NoC and to create tests to validate the behavior of the hardware models.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences:

  • At least basic programming skills in a hardware description language i.e. VHDL or (System)Verilog
  • Solid Python programming skills
  • At least basic knowledge of the functionality of NoCs
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • understand the concept of TDM NoCs
  • understand the concept of fault-detection in hardware
  • create and extend hardware modules in SystemVerilog
  • create tests to validate hardware modules
  • document your work in form of a scientific report and a presentation

 

Contact

Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de

Supervisor:

Forschung

Ich forsche an fehlertoleranten Network on Chips (NoC) für sicherheitskritische Echtzeitsysteme. Dabei konzentriere ich mich insbesondere auf Time-Division Multiplexed (TDM) und hybride NoCs.

Projekte

Open Source Projekte

  • OpTiMSoC
    A free and open framework for tiled manycore SoCs
  • GLIP: the Generic Logic Interfacing Library
    Simple, FIFO-based communication between FPGA and a PC

Publikationen

(No documents in this view)