Andreas Oeldemann, M.Sc.

Wissenschaftlicher Mitarbeiter  

Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München

Tel.: +49.89.289.22962
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2137
Email: andreas.oeldemann@tum.de

Willkommen auf meiner Website am Lehrstuhl für Integrierte Systeme!

Ich bin ein Ingenieur der Elektrotechnik mit umfangreichem Know-How in den Bereichen Rechnerarchitektur, Computernetzwerke und FPGA Hardwareentwicklung. Momentan arbeite ich am Lehrstuhl für Integrierte Systeme als wisschenschaftlicher Mitarbeiter und Doktorand. Meine Forschung befasst sich primär mit der Steigerung der Ressourcen- und Energieeffizienz in modernen Data Center Netzwerken. Wenn Sie mehr über meine Arbeit erfahren möchten, finden Sie unten eine Beschreibung.

Ich bin immer auf der Suche nach qualifizierten Studenten, die meine Interessen im Bereich Netzwerkprozessierung teilen und mit mir in diesem Bereich im Rahmen einer Master- oder Bachelorarbeit zusammenarbeiten wollen. Kontaktieren Sie mich gerne per Telefon, E-Mail oder persönlich in meinem Büro!

Lebenslauf

  • Doktorand am LIS seit 2014
  • B.Sc. und M.Sc. in Elektro- und Informationstechnik an der TUM
  • Werkstudent während des Studiums bei Infineon und Intel Mobile Communications

Lehre

Betreute Arbeiten

  • Integration of Security Functions into an FPGA-based P4 Network Processing Pipeline
    (Masterarbeit, Fabian Pusch, 2018)
  • Design and Implementation of an FPGA-based Network Interface Card using the Coherent Accelerator Processor Interface
    (Masterarbeit, Malavika Krishnaswamy, 2018)
  • Entwurf und Implementierung eines FPGA basierten Transceivers
    (Externe Bachelorarbeit, Batuhan Kurunc, 2018)
  • Extending a simulation model of a load management layer to take offload decisions based on latency predictions
    (Forschungspraxis, Spyridon Poursalidis, 2018)
  • Software-Defined Network Packet Classification on FPGAs
    (Externe Masterarbeit, Goekhan Kaplayan, 2017)
  • Load Management for Stateful Virtualized Network Functions
    (Forschungspraxis, Yanqin Li, 2017)
  • Extension of an FPGA-based network tester to support continuous replay of large network traces
    (Bachelorarbeit, Stefan Keller, 2017)
  • Untersuchung der Energieeffizienz von Data Plane Development Kit Netzwerkapplikationen
    (Bachelorarbeit, Thomas Göttsberger, 2017)
  • Increasing the resource consumption efficiency of an FPGA-based network tester to expand the generation of traffic patterns
    (Bachelorarbeit, Spyridon Poursalidis, 2017)
  • Extension of an FPGA-based network tester to measure transient throughput and latency variations of Ethernet networks
    (Masterarbeit, Andreas Ring, 2016)
  • Design and Implementation of IP based Communication Protocol and Control Function for a Signal Generator
    (Externe Masterarbeit, Sudhanshu Jiteshkumar Vora, 2016)
  • Erweiterung eines FPGA-Netzwerktesters zur Generierung von TCP Traffic
    (Bachelorarbeit, Andreas Hanus, 2016)
  • Prototype for Pre-Silicon SW-HW Co-Verification of Mobile Device Protocol Stack Drivers
    (Externe Masterarbeit, Sharath Chandra, 2015)

Angebotene Arbeiten

BAMAIDPFPIPHSSHK
Titel
------

Extensions & Performance Benchmarks of a CAPI-based Network Interface Card

Extensions & Performance Benchmarks of a CAPI-based Network Interface Card

Beschreibung

With ever-increasing network data rates, the data transfer between network interface card (NIC) and the host system has a decisive impact on the achievable application performance. To fully exploit the host system’s CPU capacity for application processing, it is important to minimize I/O processing overheads. In this project, we want to extend the implementation and optimize the performance of an FPGA-based NIC that is connected to the host system with the Coherent Accelerator Processor Interface (CAPI) [1] for IBM POWER8 Systems.

In a previous project an initial implementation of the CAPI-based NIC was developed using the CAPI Storage, Network and Analytics Programming (SNAP) framework [2]. The goal of this project is to integrate the physical network interfaces in the design, as well as to identify and mitigate performance bottlenecks.

[1] https://developer.ibm.com/linuxonpower/capi/

[2] https://openpowerfoundation.org/blogs/capi-snap-simple-developers

Towards this goal you will complete the following tasks:

  • Analyze source code and working principles of the existing NIC implementation
  • Getting familiar with CAPI and the CAPI SNAP framework
  • Integrate an Ethernet Media Access Controller (MAC) IP core into the FPGA design
  • Benchmark throughput and latency of FPGA-to-host communication through simulations and measurements
  • Identify performance bottlenecks, propose and implement improvements
  • Extend the design to make use of multiple RX/TX queues for multi-core processing

Voraussetzungen

To successfully complete this project, you should already have several of the following skills and experiences:

  • Knowledge of a hardware description language such as Verilog and/or VHDL
  • Hands-on FPGA development experience
  • Solid C programming skills
  • Proficiency using Linux
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • understand the basic working principles of NICs, as well as FPGA-host communication mechanisms
  • apply your theoretical knowledge to an implementation consisting of both hard- and software parts
  • document work in a scientific report form and in a presentation

Kontakt

Andreas Oeldemann
Room N2137
Tel. 089 289 22962
andreas.oeldemann@tum.de

The thesis is carried out in cooperation with

Power Systems Acceleration Department
IBM Systems – HW Development Böblingen
IBM Deutschland R&D GmbH

 

 

Betreuer:

Laufende Arbeiten

Publikationen

  • Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf: FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet. International Conference on Field-Programmable Logic and Applications (FPL), 2018 mehr… BibTeX
  • Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf: Reducing Data Center Resource Over-Provisioning Through Dynamic Load Management for Virtualized Network Functions. International Conference on Architecture of Computing Systems, 2017 mehr… BibTeX Volltext ( DOI )
  • Michael Vonbun, Stefan Wallentowitz, Andreas Oeldemann, Andreas Herkersdorf: An Analytic Approach on End-to-end Packet Error Rate Estimation for Network-on-Chip. Euromicro Conference on Digital System Design (DSD), 2015 mehr… BibTeX