Andreas Oeldemann, M.Sc.

Wissenschaftlicher Mitarbeiter  

Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München

Tel.: +49.89.289.22962
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2137
Email: andreas.oeldemann@tum.de

Angebotene Arbeiten

BAMAIDPFPIPHSSHK
Title
------

Extensions & Performance Benchmarks of a CAPI-based Network Interface Card

Extensions & Performance Benchmarks of a CAPI-based Network Interface Card

Description

With ever-increasing network data rates, the data transfer between network interface card (NIC) and the host system has a decisive impact on the achievable application performance. To fully exploit the host system’s CPU capacity for application processing, it is important to minimize I/O processing overheads. In this project, we want to extend the implementation and optimize the performance of an FPGA-based NIC that is connected to the host system with the Coherent Accelerator Processor Interface (CAPI) [1] for IBM POWER8 Systems.

In a previous project an initial implementation of the CAPI-based NIC was developed using the CAPI Storage, Network and Analytics Programming (SNAP) framework [2]. The goal of this project is to integrate the physical network interfaces in the design, as well as to identify and mitigate performance bottlenecks.

[1] https://developer.ibm.com/linuxonpower/capi/

[2] https://openpowerfoundation.org/blogs/capi-snap-simple-developers

Towards this goal you will complete the following tasks:

  • Analyze source code and working principles of the existing NIC implementation
  • Getting familiar with CAPI and the CAPI SNAP framework
  • Integrate an Ethernet Media Access Controller (MAC) IP core into the FPGA design
  • Benchmark throughput and latency of FPGA-to-host communication through simulations and measurements
  • Identify performance bottlenecks, propose and implement improvements
  • Extend the design to make use of multiple RX/TX queues for multi-core processing

Prerequisites

To successfully complete this project, you should already have several of the following skills and experiences:

  • Knowledge of a hardware description language such as Verilog and/or VHDL
  • Hands-on FPGA development experience
  • Solid C programming skills
  • Proficiency using Linux
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • understand the basic working principles of NICs, as well as FPGA-host communication mechanisms
  • apply your theoretical knowledge to an implementation consisting of both hard- and software parts
  • document work in a scientific report form and in a presentation

Contact

Andreas Oeldemann
Room N2137
Tel. 089 289 22962
andreas.oeldemann@tum.de

The thesis is carried out in cooperation with

Power Systems Acceleration Department
IBM Systems – HW Development Böblingen
IBM Deutschland R&D GmbH

 

 

Supervisor:

Laufende Arbeiten

Publikationen

  • Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf: FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet. International Conference on Field-Programmable Logic and Applications (FPL), 2018 more… BibTeX
  • Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf: Reducing Data Center Resource Over-Provisioning Through Dynamic Load Management for Virtualized Network Functions. International Conference on Architecture of Computing Systems, 2017 more… BibTeX Full text ( DOI )
  • Michael Vonbun, Stefan Wallentowitz, Andreas Oeldemann, Andreas Herkersdorf: An Analytic Approach on End-to-end Packet Error Rate Estimation for Network-on-Chip. Euromicro Conference on Digital System Design (DSD), 2015 more… BibTeX