Sven Rheindt, M.Sc.

Wissenschaftlicher Mitarbeiter  

Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Integrierte Systeme
Arcisstr. 21
80290 München

Tel.: +49.89.289.28387
Fax: +49.89.289.28323
Gebäude: N1 (Theresienstr. 90)
Raum: N2140
E-mail: sven.rheindt@tum.de

Lebenslauf

  • Am LIS seit 2016
  • B.Sc & M.Sc EI an der TUM
  • 12 Monate in der FPGA Entwicklungsabteilung bei ARRI (BA, FP, MA)
  • 1 Semester an der Georgia Tech

Lehre

Studentische Arbeiten

Info:

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Angebotene Arbeiten

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Title
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Design and Implementation of a Hardware Managed Queue

Design and Implementation of a Hardware Managed Queue

Description

Description

Queues are a central element of an Operating System and Application Control Flow in general.

This project is part of a hardware-software codesign.

Goal

The goal of this project is to develop a hardware managed queue for a NoC-based multiprocessor platform

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Very good programming skills VHDL
  • Good comprehension of a complex system
  • Good knowledge about hardware development.
  • Very good knowledge about digital circuit design

Contact

Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de

Supervisor:

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Application Profiling for Near Memory Computing

Application Profiling for Near Memory Computing

Description

* Image Source: http://www.layer7.co.za/app_profiling.html

Description

Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.

The newest trend to tackle this issue is data-task migration and processing in or near memory.

Goal

The goal of this project is to profile application in the context of Near Memory Computing and to identify useful functions or primitives that could be accelerated.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Very good programming skills in C/C++
  • Good programming skills in SystemC
  • Very good analytical thinking and understanding of complex problems
  • Good knowledge about digital circuit design
  • Very good knowledge in the field of Near Memory Computing

Contact

Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de

Supervisor:

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FPGA Prototyping a Bus Front-End for Near Memory Accelerators

FPGA Prototyping a Bus Front-End for Near Memory Accelerators

Description

Description

Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.

The newest trend to tackle this issue is data-task migration and processing in or near memory.

Goal

The goal of this project is to develop a bus front-end for near memory operations on a FPGA prototype.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Very good programming skills VHDL
  • Good comprehension of a complex system
  • Good knowledge about hardware development.
  • Very good knowledge about digital circuit design

Contact

Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de

Supervisor:

-

FPGA Prototyping a Memory Back-End for Near Memory Accelerators

FPGA Prototyping a Memory Back-End for Near Memory Accelerators

Description

Description

Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.

The newest trend to tackle this issue is data-task migration and processing in or near memory.

Goal

The goal of this project is to develop a memory back-end for near memory operations on a FPGA prototype.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Very good programming skills VHDL
  • Good comprehension of a complex system
  • Good knowledge about hardware development.
  • Very good knowledge about digital circuit design

Contact

Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de

Supervisor:

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Frequency Optimization of a FPGA Prototype

Frequency Optimization of a FPGA Prototype

Description

Description

Our NoC-based many-core design is implemented on multiple Xilinx Virtex7 FPGAs. It is currently frequency limited by individual components.

Goal

The goal of this work is to optimize the overall frequency of an FPGA design.

This work includes:

  • Indetification of the critical paths of the design
  • Pipelining the design to reach higher frequencies

Prerequisites

For this challenging task, several prerequisites should be met:

  • Very good knowledge of VHDL
  • Very good knowledge of the Xilinx Vivado Synthesis Tool
  • Very good experience with FPGA design
  • Very good knowledge about digital circuit design

Application

If you are interested, send me an email with your CV, your transcript of records and summary of your experience attachted.

Contact

Sven Rheindt

Room: N2140

Tel. 089 289 28387

sven.rheindt@tum.de

Supervisor:

-

Simulator Support for Dynamic Task Migration

Simulator Support for Dynamic Task Migration

Description

Description

Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.

The newest trend to tackle this issue is data-task migration and processing in or near memory.

Goal

The goal of this project is to implement dynamic data migration into a trace-based simulator and to evaluate its potential.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Very good programming skills in C++ or SystemC
  • Good comprehension of a complex system
  • Very good knowledge about hardware development.

Contact

Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de

Supervisor:

Laufende Arbeiten

Student Assistant Jobs

Studentische Hilfskraft für Vorlesung Digitale Schaltungen

Studentische Hilfskraft für Vorlesung Digitale Schaltungen

Description

Die Tätigkeit umfasst 

  • Vorkorrektur von Hausaufgaben und praktischen Übungen
  • 2 ngSpice Tutorstunden zu den praktischen Übungen

Contact

Sven Rheindt

Room: N2140

Tel. 089 289 28387

sven.rheindt@tum.de

Supervisor:

Betreute Arbeiten

  • Improving and Evaluating the Simulation Environment for Dynamic Data Migration
    (Bachelorarbeit, Jonas Kirf, 2018)
  • Implementation of Advanced Graphcopy Features and the Development of a Testsuite
    (Forschungspraxis, Oliver Lenke, 2018)
  • Design and Implementation of a Near Memory Graphcopy Accelerator
    (Forschungspraxis, Lars Nolte, 2018)
  • Design and Implementation of a Near-Memory Accelerator Simulation Framework
    (Forschungspraxis, Matthias Engelhard, 2018)
  • Efficiant Management of Network Function in NoC based Multicore Systems
    (Master Thesis, Steffen Schlienz, 2018)
  • Research on and Implementation of a Hardware-Managed Queue
    (Forschungspraxis, Alexander Preißner, 2018)
  • Design of a Near Memory Accelerator Concept for Distributed Shared Memory Architectures
    (Bachelorarbeit, Oliver Lenke, 2018)
  • Implementation and Evaluation of a Generic DMA Controller on a Distributed Shared Memory Architecture
    (Bachelorarbeit, Lars Nolte, 2018)
  • Simulator Support for Dynamic Data Migration
    (Masterarbeit, Iffat Brekhna, 2018)
  • Improving Synchronization for Distributed Memory Systems
    (Werkstudent, Andreas Schenk, 2018)
  • Address Translation Unit - enabling a global address space for invasive computing
    (Bachelorarbeit, Emin Saidi, 2017)
  • Address Map Protection on a Tiled Multi-Processor Platform
    (Forschungspraxis, Alexander Gembarzhevskiy, 2016)
  • Design and Implementation of a Compare-and-Swap (CAS) Instruction over a Network on Chip (NoC)

    (Forschungspraxis, Andreas Schenk, 2016)

Forschung

Projekte

Invasive Computing (SFB/TR 89)

  • Teilprojekt B5 - Memory Hierarchy
  • Teilprojekt Z2 - FPGA Integration, Validation & Demonstrator

Interessen

Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades. Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.

The newest trend to tackle this issue is data-task migration and processing in or near memory.

Publikationen

  • Sven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild and Andreas Herkersdorf: CaCAO: Complex and Compositional Atomic Operations for NoC-based Manycore Platforms. ARCS 2018 - 31st International Conference on Architecture of Computing Systems, 2018 more… BibTeX
  • Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf: Region Based Cache Coherence for Tiled MPSoCs. 2017 30th IEEE International System-on-Chip Conference (SOCC), 2017 more… BibTeX