Forschungspraxis oder MSCE Forschungspraxis

Development of a Monitoring & Fault Injection Infrastructure for an MPSoC Demonstrator Featuring a Hybrid NoC

Development of a Monitoring & Fault Injection Infrastructure for an MPSoC Demonstrator Featuring a Hybrid NoC

Beschreibung

Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
For an MPSoC based demonstrator that is intended to demonstrate fail-operational capabilities (e.g. for automotive use cases) it is necessary to not only monitor and display the current state of the system but also inject faults into the system as well.

Goal

The goal of this work is to develop an infrastructure to monitor the traffic load and task execution in an MPSoC on an FPGA, inject faults in the system’s NoC, and provide a GUI on a host PC to display the system’s status and control the fault injection. This work can be split in several work packets.

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences:

  • Good programming skills in either a hardware description language i.e. (System)Verilog or VHDL and/or C and JavaScript (or another programming language of your choice to create a GUI)
  • Solid Python programming skills
  • At least basic knowledge of the functionality of NoCs
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • Understand the concept of TDM NoCs
  • Create and extend hardware modules in SystemVerilog
  • Create tests to validate hardware modules
  • Create and extend software on a host PC that communicates with hardware modules on an FPGA
  • Document your work in form of a scientific report and a presentation

 

 

Kontakt

Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de

Betreuer:

Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype

Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype

Stichworte:
Cache Coherence, Distributed Shared Memory MPSoCs

Kurzbeschreibung:
The goal of this project is to extend RBCC to global memory with distributed directories.

Beschreibung

Providing hardware coherence formoderntile-based MPSoCsrequires additional area. As a result, this does not scale with increasing tile counts.As part of the Invasive Computing project, we introducedRegion Based Cache Coherence (RBCC) whichis ascalableapproachthat provides on-demand coherence. RBCC enables users to dynamically create/destroy coherency regions based on application requirements. Currently, RBCC has been developed for the distributed tile local memories of our system. The next step is to extend RBCC to the global memory, so as to fully utilize the memory capacity of our heterogeneous muticore architecture.

Towards this goal you’ll complete the following tasks:

  • Investigate existing distributed directory based cache coherence schemes

  • Extend RBCC to global DDR memory

  • Verify the design on a FPGA-based hardware platform

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences.

  • Very Good VHDL Skills

  • Good C/C++ Skills

  • Good understanding of MPSoCs and Cache Coherence Schemes

  • Self-motivated and structured work style

 

 

Kontakt

Akshay Srivatsa
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 22963
srivatsa.akshay@tum.de
www.lis.ei.tum.de

Betreuer:

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