Forschungspraxis oder MSCE Forschungspraxis

Design of a HW-Debugger for a self-aware SoC paradigm based on hardware machine learning (IPF)

Design of a HW-Debugger for a self-aware SoC paradigm based on hardware machine learning (IPF)

Stichworte:
Machine Learning, Supervisory control theory, Learning Classifier system, HW Debugger, VHDL, SoC, C, Matlab

Kurzbeschreibung:
The goal of this project is to develop a hardware debugger for the machine learning based IPF platform.

Beschreibung

Today's Multi-Processor System-on-Chip (MPSoCs) are getting more and more complex due to the growing amount of cores and accelerators.  Hence it's not possible anymore to set runtime parameters like frequency and task distribution by design time in an optimal manner. Therefore future controllers try to make use of machine learning which is aware of the system's current state (self-awareness).

Information Processing Factoriy (IPF) is a global project that claims to show self-awareness across multiple abstraction levels. It represents a paradigm shift in platform design by envisioning the move towards a consistent platform-centric design in which the combination of self-organized learning and formal reactive methods guarantee the applicability of such cyber-physical systems in safety-critical and high-availability applications.

At TUM, we explore the application and implementation of machine learning algorithms in hardware to optimize the mode of operation of MPSoCs at runtime. 

Towards this goal, you'll complete the following tasks:
1. Understand the current implementation of Learning Classifier Tables (LCT) and Supervisory Control as well as their communication with SW and our GUI in VHDL.
2. Design and implement a new HW debugger, which can provide measurement values at a higher rate than the current SW debugger and which doesn't interfere with benchmarks executed on the cores.
3. Verify the interplay between GUI and your HW debugger.

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences:
• Good VHDL Skills
• Good C / C ++ Skills
• Good Matlab Skills
• Good Understanding of MPSoCs
• Self-motivated and structured work style
• opional: basic knowledge of machine learning

Kontakt

Florian Maurer
Chair of Integrated Systems 
Arcisstrasse 21, 80333 Munich Germany
Tel. +49 89 289 23870 
flo.maurer@tum.de
www.lis.ei.tum.de

 

Anmol Prakash Surhonne
Chair of Integrated Systems
Arcisstrasse 21, 80333 Munich Germany
Tel. +49 89 289 23872
anmol.surhonne@tum.de
www.lis.ei.tum.de 

Betreuer:

Florian Maurer, Anmol Prakash Surhonne

Development of a Monitoring & Fault Injection Infrastructure for an MPSoC Demonstrator Featuring a Hybrid NoC

Development of a Monitoring & Fault Injection Infrastructure for an MPSoC Demonstrator Featuring a Hybrid NoC

Beschreibung

Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
For an MPSoC based demonstrator that is intended to demonstrate fail-operational capabilities (e.g. for automotive use cases) it is necessary to not only monitor and display the current state of the system but also inject faults into the system as well.

Goal

The goal of this work is to develop an infrastructure to monitor the traffic load and task execution in an MPSoC on an FPGA, inject faults in the system’s NoC, and provide a GUI on a host PC to display the system’s status and control the fault injection. This work can be split in several work packets.

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences:

  • Good programming skills in either a hardware description language i.e. (System)Verilog or VHDL and/or C and JavaScript (or another programming language of your choice to create a GUI)
  • Solid Python programming skills
  • At least basic knowledge of the functionality of NoCs
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • Understand the concept of TDM NoCs
  • Create and extend hardware modules in SystemVerilog
  • Create tests to validate hardware modules
  • Create and extend software on a host PC that communicates with hardware modules on an FPGA
  • Document your work in form of a scientific report and a presentation

 

 

Kontakt

Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de

Betreuer:

Development of an Evaluation Tool to Evaluate and Visualize Simulation Results of a Hybrid NoC Simulator

Development of an Evaluation Tool to Evaluate and Visualize Simulation Results of a Hybrid NoC Simulator

Beschreibung

Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift to wards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
A specific kind of NoC, specifically a hybrid TDM and packet-switched NoC, is evaluated with an in-house cycle-accurate simulation model. Processing, evaluating, and visualizing the results of such a simulation in a comprehensible manner is a difficult task in itself.

Goal

The goal of this work is to develop a tool to evaluate, compare, and visualize the results of a simulation model of a hybrid TDM and packet-switched NoC.

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences:

  • Good programming skills in Python and JavaScript (or another programming language of your choice to create a GUI)
  • At least basic knowledge of the functionality of NoCs
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • Understand the concept of TDM NoCs
  • Create and extend software tools to process, evaluate, and visualize large amounts of data in a com-
    prehensible manner
  • Document your work in form of a scientific report and a presentation

 

 

Kontakt

Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de

Betreuer:

Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype

Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype

Stichworte:
Cache Coherence, Distributed Shared Memory MPSoCs

Kurzbeschreibung:
The goal of this project is to extend RBCC to global memory with distributed directories.

Beschreibung

Providing hardware coherence formoderntile-based MPSoCsrequires additional area. As a result, this does not scale with increasing tile counts.As part of the Invasive Computing project, we introducedRegion Based Cache Coherence (RBCC) whichis ascalableapproachthat provides on-demand coherence. RBCC enables users to dynamically create/destroy coherency regions based on application requirements. Currently, RBCC has been developed for the distributed tile local memories of our system. The next step is to extend RBCC to the global memory, so as to fully utilize the memory capacity of our heterogeneous muticore architecture.

Towards this goal you’ll complete the following tasks:

  • Investigate existing distributed directory based cache coherence schemes

  • Extend RBCC to global DDR memory

  • Verify the design on a FPGA-based hardware platform

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences.

  • Very Good VHDL Skills

  • Good C/C++ Skills

  • Good understanding of MPSoCs and Cache Coherence Schemes

  • Self-motivated and structured work style

 

 

Kontakt

Akshay Srivatsa
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 22963
srivatsa.akshay@tum.de
www.lis.ei.tum.de

Betreuer:

Design and Implementation of a Hardware Managed Queue

Design and Implementation of a Hardware Managed Queue

Beschreibung

Description

Queues are a central element of an Operating System and Application Control Flow in general.

This project is part of a hardware-software codesign.

Goal

The goal of this project is to develop a hardware managed queue for a NoC-based multiprocessor platform

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Very good programming skills VHDL
  • Good comprehension of a complex system
  • Good knowledge about hardware development.
  • Very good knowledge about digital circuit design

Contact

Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de

Betreuer:

Application Profiling for Near Memory Computing

Application Profiling for Near Memory Computing

Beschreibung

* Image Source: http://www.layer7.co.za/app_profiling.html

Description

Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.

The newest trend to tackle this issue is data-task migration and processing in or near memory.

Goal

The goal of this project is to profile application in the context of Near Memory Computing and to identify useful functions or primitives that could be accelerated.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Very good programming skills in C/C++
  • Good programming skills in SystemC
  • Very good analytical thinking and understanding of complex problems
  • Good knowledge about digital circuit design
  • Very good knowledge in the field of Near Memory Computing

Contact

Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de

Betreuer:

FPGA Prototyping a Bus Front-End for Near Memory Accelerators

FPGA Prototyping a Bus Front-End for Near Memory Accelerators

Beschreibung

Description

Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.

The newest trend to tackle this issue is data-task migration and processing in or near memory.

Goal

The goal of this project is to develop a bus front-end for near memory operations on a FPGA prototype.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Very good programming skills VHDL
  • Good comprehension of a complex system
  • Good knowledge about hardware development.
  • Very good knowledge about digital circuit design

Contact

Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de

Betreuer:

FPGA Prototyping a Memory Back-End for Near Memory Accelerators

FPGA Prototyping a Memory Back-End for Near Memory Accelerators

Beschreibung

Description

Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.

The newest trend to tackle this issue is data-task migration and processing in or near memory.

Goal

The goal of this project is to develop a memory back-end for near memory operations on a FPGA prototype.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Very good programming skills VHDL
  • Good comprehension of a complex system
  • Good knowledge about hardware development.
  • Very good knowledge about digital circuit design

Contact

Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de

Betreuer:

Simulator Support for Dynamic Task Migration

Simulator Support for Dynamic Task Migration

Beschreibung

Description

Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.

The newest trend to tackle this issue is data-task migration and processing in or near memory.

Goal

The goal of this project is to implement dynamic data migration into a trace-based simulator and to evaluate its potential.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences.

  • Very good programming skills in C++ or SystemC
  • Good comprehension of a complex system
  • Very good knowledge about hardware development.

Contact

Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de

Betreuer:

Laufende Arbeiten

Forschungspraxis oder MSCE Forschungspraxis

False-Sharing Resolution: A Hardware Mechanism to Detect & Resolve False-Sharing for Region Based Cache Coherence

False-Sharing Resolution: A Hardware Mechanism to Detect & Resolve False-Sharing for Region Based Cache Coherence

Stichworte:
Cache Coherence, Distributed Shared Memory MPSoCs

Kurzbeschreibung:
The goal of this project is to detect & resolve false-sharing of cache lines in a Distributed Shared Memory MPSoC

Beschreibung

Providing hardware coherence for modern tile-based MPSoCs requires additional area. As a result, this does not
scale with increasing tile counts. As part of the Invasive Computing project, we introduced Region Based Cache
Coherence (RBCC) which is a scalable approach that provides on-demand coherence. RBCC enables users to
dynamically create/destroy coherency regions based on application requirements. RBCC is transparently enabled
using a highly modular Coherency Region Manager (CRM) module attached on the bus. The non-intrusiveness of
the CRM combined with NUMA properties can result in false-sharing of cache blocks. False-sharing not only
degrades performance but can also corrupt data. False-sharing can be easily alleviated by software alignment at
the cost of memory, therefore a hardware solution is preferred.

Towards this goal you’ll complete the following tasks:
• Investigate existing directory based cache coherence schemes
• Investigate the false-sharing problem and its possible solutions
• Implement a hardware mechanism to resolve false-sharing for RBCC
• Verify the design on a FPGA-based hardware platform

Voraussetzungen

To successfully complete this project, you should already have the following skills and
experiences.
• Very Good VHDL Skills
• Good C/C++ Skills
• Good understanding of MPSoCs and Cache Coherence Schemes
• Self-motivated and structured work style

Kontakt

Akshay Srivatsa
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 22963
srivatsa.akshay@tum.de
www.lis.ei.tum.de

Betreuer:

HW-SW interface design for a self-aware SoC paradigm based on hardware machine learning (IPF)

HW-SW interface design for a self-aware SoC paradigm based on hardware machine learning (IPF)

Stichworte:
Machine Learning, Supervisory control theory, Learning Classifier system, HW-SW Interface, VHDL, C, SoC

Kurzbeschreibung:
The goal of this project is to develop a hardware-software interface for the machine learning based IPF platform.

Beschreibung

As today's Multi-Processor System-on-Chip (MPSoCs) are getting more and more complex due to the growing amount of cores and accelerators.  Hence it's not possible anymore to set runtime parameters like frequency and task distribution by design time in an optimal manner. Therefore future controllers try to make use of machine learning which is aware of the system's current state (self-awareness).

Information Processing Factoriy (IPF) is a global project that claims to show self-awareness across multiple abstraction levels. It represents a paradigm shift in platform design by envisioning the move towards a consistent platform-centric design in which the combination of self-organized learning and formal reactive methods guarantee the applicability of such cyber-physical systems in safety-critical and high-availability applications.

At TUM, we explore the application and implementation of machine learning algorithms in hardware to optimize the mode of operation of MPSoCs at runtime. 

Towards this goal, you'll complete the following tasks:
1. Understand the current implementation of Learning Classifier Tables (LCT) and Supervisory Control as well as their communication with SW in VHDL.
2. Design and implement a new HW-SW interface which supports new features and functionalities on the FPGA.
3. Develop a software API to utilize the functionalities implemented in hardware.
4. Test your new HW-SW interface.

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences:
• Good VHDL Skills
• Good C / C ++ Skills
• Good Understanding of MPSoCs
• Self-motivated and structured work style
• opional: basic knowledge of machine learning

Kontakt

Anmol Prakash Surhonne
Chair of Integrated Systems
Arcisstrasse 21, 80333 Munich Germany
Tel. +49 89 289 23872
anmol.surhonne@tum.de
www.lis.ei.tum.de 

Florian Maurer
Chair of Integrated Systems
Arcisstrasse 21, 80333 Munich Germany
Tel. +49 89 289 23870
flo.maurer@tum.de
www.lis.ei.tum.de

Betreuer:

Anmol Prakash Surhonne, Florian Maurer