
Software Partitioning and Scheduling (at GE Aviation)
Software Partitioning and Scheduling (at GE Aviation)
Beschreibung
This work is an offer of General Electric Aviation supervised at TUM LIS.
About GE Aviation
GE Aviation Munich is a R&D center of excellence and is in the heart of southern Germany, on the Garching campus of the Technical University of Munich. This creates a unique blend for our engineers to be in a university setting, while performing research and development in a world-class industrial environment that is dedicated to bringing innovative technologies to market. Within the R&D community, the center maintains close partnerships with numerous universities, research institutions and technology companies in Germany and abroad.
Role summary
GE Aviation is investigating the use of modern multi-core architectures. You will migrate existing singlecore software to a multi-core platform. This work focuses on partitioning of existing software, deployment and schedule synthesis to maximize processor utilization. This work can be done either as a student job or for your master thesis.
Responsibilities
- Determine tasks that can be run in parallel without impacting data flow and introducing data latency.
- Develop an automated method for partitioning, deployment and scheduling based on a variety of
tools. - Demonstrate scalability, usability and determinismof the selected solution.
Expected Qualifications
- Good Java/C/C++ Skills
- Good understanding of task scheduling
- First experience with development of toolchains
- Self-motivated, structured work style and good communication skills
- Fluency in English
- Good academic track record
Kontakt
Supervisor at GE Aviation: Alexander Walsch
Betreuer:

Development of a Monitoring & Fault Injection Infrastructure for an MPSoC Demonstrator Featuring a Hybrid NoC
Development of a Monitoring & Fault Injection Infrastructure for an MPSoC Demonstrator Featuring a Hybrid NoC
Beschreibung
Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
For an MPSoC based demonstrator that is intended to demonstrate fail-operational capabilities (e.g. for automotive use cases) it is necessary to not only monitor and display the current state of the system but also inject faults into the system as well.
Goal
The goal of this work is to develop an infrastructure to monitor the traffic load and task execution in an MPSoC on an FPGA, inject faults in the system’s NoC, and provide a GUI on a host PC to display the system’s status and control the fault injection. This work can be split in several work packets.
Voraussetzungen
To successfully complete this project, you should already have the following skills and experiences:
- Good programming skills in either a hardware description language i.e. (System)Verilog or VHDL and/or C and JavaScript (or another programming language of your choice to create a GUI)
- Solid Python programming skills
- At least basic knowledge of the functionality of NoCs
- Self-motivated and structured work style
Learning Objectives
By completing this project, you will be able to
- Understand the concept of TDM NoCs
- Create and extend hardware modules in SystemVerilog
- Create tests to validate hardware modules
- Create and extend software on a host PC that communicates with hardware modules on an FPGA
- Document your work in form of a scientific report and a presentation
Kontakt
Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de
Betreuer:

Development of a Concept to Enable Access to Heavily Shared Resources in an MPSoC Featuring a Hybrid NoC
Development of a Concept to Enable Access to Heavily Shared Resources in an MPSoC Featuring a Hybrid NoC
Beschreibung
Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
One way of organizing the access to such a NoC is by using Time-Division Multiplexing (TDM) which allows to give service guarantees. However, in a TDM NoC the number of parallel accesses to a resource is limited which is problematic for heavily shared resources such as memory and I/O.
Goal
The goal of this thesis is to develop a concept to enable access to heavily shared resources for critical applica tions using TDM traffic in a hybrid TDM and packet-switched NoC.
Voraussetzungen
To successfully complete this project, you should already have the following skills and experiences:
- Good programming skills in a hardware description language i.e. (System)Verilog or VHDL
- Good knowledge of on-chip communication
- Solid Python programming skills
- At least basic knowledge of the functionality of NoCs
- Self-motivated and structured work style
Learning Objectives
By completing this project, you will be able to
- Understand the concept of TDM NoCs
- Create and extend hardware modules in SystemVerilog
- Create tests to validate hardware modules
- Document your work in form of a scientific report and a presentation
Kontakt
Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de
Betreuer:

Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype
Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype
Stichworte:
Cache Coherence, Distributed Shared Memory MPSoCs
Kurzbeschreibung:
The goal of this project is to extend RBCC to global memory with distributed directories.
Beschreibung
Providing hardware coherence formoderntile-based MPSoCsrequires additional area. As a result, this does not scale with increasing tile counts.As part of the Invasive Computing project, we introducedRegion Based Cache Coherence (RBCC) whichis ascalableapproachthat provides on-demand coherence. RBCC enables users to dynamically create/destroy coherency regions based on application requirements. Currently, RBCC has been developed for the distributed tile local memories of our system. The next step is to extend RBCC to the global memory, so as to fully utilize the memory capacity of our heterogeneous muticore architecture.
Towards this goal you’ll complete the following tasks:
-
Investigate existing distributed directory based cache coherence schemes
-
Extend RBCC to global DDR memory
-
Verify the design on a FPGA-based hardware platform
Voraussetzungen
To successfully complete this project, you should already have the following skills and experiences.
-
Very Good VHDL Skills
-
Good C/C++ Skills
-
Good understanding of MPSoCs and Cache Coherence Schemes
-
Self-motivated and structured work style
Kontakt
Akshay Srivatsa
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 22963
srivatsa.akshay@tum.de
www.lis.ei.tum.de
Betreuer:

Evaluation of a new European FPGA technology ("Brave") for space mass memory (at Airbus in Friedrichshafen)
Evaluation of a new European FPGA technology ("Brave") for space mass memory (at Airbus in Friedrichshafen)
Beschreibung
- Evaluation of the "Brave Large" FPGA technology in terms of the impact for current space mass memory FPGA architectures
- Perform the portability assessment of a space mass memory applications to the new FPGA technology, make use of the
available on-chip ARM Cortex R5 core if necessary
- Demonstrate the performance of the application with an implementation on the simulation tools and in hardware
- Evaluation of tool chain (Synthesis and Place and Route) for this technology
- Documentation of all the evaluation, implementation, various analysis and test results.
Betreuer:

Extensions & Performance Benchmarks of a CAPI-based Network Interface Card
Extensions & Performance Benchmarks of a CAPI-based Network Interface Card
Beschreibung
With ever-increasing network data rates, the data transfer between network interface card (NIC) and the host system has a decisive impact on the achievable application performance. To fully exploit the host system’s CPU capacity for application processing, it is important to minimize I/O processing overheads. In this project, we want to extend the implementation and optimize the performance of an FPGA-based NIC that is connected to the host system with the Coherent Accelerator Processor Interface (CAPI) [1] for IBM POWER8 Systems.
In a previous project an initial implementation of the CAPI-based NIC was developed using the CAPI Storage, Network and Analytics Programming (SNAP) framework [2]. The goal of this project is to integrate the physical network interfaces in the design, as well as to identify and mitigate performance bottlenecks.
[1] https://developer.ibm.com/linuxonpower/capi/
[2] https://openpowerfoundation.org/blogs/capi-snap-simple-developers
Towards this goal you will complete the following tasks:
- Analyze source code and working principles of the existing NIC implementation
- Getting familiar with CAPI and the CAPI SNAP framework
- Integrate an Ethernet Media Access Controller (MAC) IP core into the FPGA design
- Benchmark throughput and latency of FPGA-to-host communication through simulations and measurements
- Identify performance bottlenecks, propose and implement improvements
- Extend the design to make use of multiple RX/TX queues for multi-core processing
Voraussetzungen
To successfully complete this project, you should already have several of the following skills and experiences:
- Knowledge of a hardware description language such as Verilog and/or VHDL
- Hands-on FPGA development experience
- Solid C programming skills
- Proficiency using Linux
- Self-motivated and structured work style
Learning Objectives
By completing this project, you will be able to
- understand the basic working principles of NICs, as well as FPGA-host communication mechanisms
- apply your theoretical knowledge to an implementation consisting of both hard- and software parts
- document work in a scientific report form and in a presentation
Kontakt
Andreas Oeldemann
Room N2137
Tel. 089 289 22962
andreas.oeldemann@tum.de
The thesis is carried out in cooperation with
Power Systems Acceleration Department
IBM Systems – HW Development Böblingen
IBM Deutschland R&D GmbH
Betreuer:

Design and Implementation of a Hardware Managed Queue
Design and Implementation of a Hardware Managed Queue
Beschreibung
Description
Queues are a central element of an Operating System and Application Control Flow in general.
This project is part of a hardware-software codesign.
Goal
The goal of this project is to develop a hardware managed queue for a NoC-based multiprocessor platform
Prerequisites
To successfully complete this project, you should already have the following skills and experiences.
- Very good programming skills VHDL
- Good comprehension of a complex system
- Good knowledge about hardware development.
- Very good knowledge about digital circuit design
Contact
Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de
Betreuer:

Interference Channel Analysis (at GE Aviation)
Interference Channel Analysis (at GE Aviation)
Beschreibung
This work is an offer of General Electric Aviation supervised at TUM LIS.
About GE Aviation
GE Aviation Munich is a R&D center of excellence and is in the heart of southern Germany, on the Garching campus of the Technical University of Munich. This creates a unique blend for our engineers to be in a university setting, while performing research and development in a world-class industrial environment that is dedicated to bringing innovative technologies to market. Within the R&D community, the center maintains close partnerships with numerous universities, research institutions and technology companies in Germany and abroad.
Role summary
GE Aviation is investigating the use of modern multi-core architectures. You will characterize the interference channels of two different multi-core architectures (NXP T1040 and Xilinx Zynq Ultrascale+). The former is a quadcore Power PC built around the e5500 core, the latter a quad-core ARM built around the A53 core. This work can be done either as a student job or for your master thesis.
Responsibilities
- Enhance an existing bare-metal test suite
- Develop a test plan
- Characterize interference channels by investigating performance and determinism
- Develop and implement mitigation concepts
Expected Qualifications
- Good C/C++ Skills
- Good understanding of MPSoCs and CPU architectures
- Experience with embedded software development
- Self-motivated, structured work style and good communication skills
- Fluency in English
- Good academic track record
Kontakt
Supervisor at GE Aviation: Alexander Walsch
Betreuer:

Application Profiling for Near Memory Computing
Application Profiling for Near Memory Computing
Beschreibung
* Image Source: http://www.layer7.co.za/app_profiling.html
Description
Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.
The newest trend to tackle this issue is data-task migration and processing in or near memory.
Goal
The goal of this project is to profile application in the context of Near Memory Computing and to identify useful functions or primitives that could be accelerated.
Prerequisites
To successfully complete this project, you should already have the following skills and experiences.
- Very good programming skills in C/C++
- Good programming skills in SystemC
- Very good analytical thinking and understanding of complex problems
- Good knowledge about digital circuit design
- Very good knowledge in the field of Near Memory Computing
Contact
Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de
Betreuer:

FPGA Prototyping a Bus Front-End for Near Memory Accelerators
FPGA Prototyping a Bus Front-End for Near Memory Accelerators
Beschreibung
Description
Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.
The newest trend to tackle this issue is data-task migration and processing in or near memory.
Goal
The goal of this project is to develop a bus front-end for near memory operations on a FPGA prototype.
Prerequisites
To successfully complete this project, you should already have the following skills and experiences.
- Very good programming skills VHDL
- Good comprehension of a complex system
- Good knowledge about hardware development.
- Very good knowledge about digital circuit design
Contact
Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de
Betreuer:

FPGA Prototyping a Memory Back-End for Near Memory Accelerators
FPGA Prototyping a Memory Back-End for Near Memory Accelerators
Beschreibung
Description
Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.
The newest trend to tackle this issue is data-task migration and processing in or near memory.
Goal
The goal of this project is to develop a memory back-end for near memory operations on a FPGA prototype.
Prerequisites
To successfully complete this project, you should already have the following skills and experiences.
- Very good programming skills VHDL
- Good comprehension of a complex system
- Good knowledge about hardware development.
- Very good knowledge about digital circuit design
Contact
Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de
Betreuer:

Simulator Support for Dynamic Task Migration
Simulator Support for Dynamic Task Migration
Beschreibung
Description
Hitting a wall is not a pleasant thing. Computer systems faced many walls in the last decades.Being able to break the memory wall in the mid 90's and the power wall in 2004, it now faces the next crucial barrier for scalabilty. Although being able to scale systems to 100's or 1000's of cores through NoCs, performance doesn't scale due to data-to-task dislocality. We now face the locality wall.
The newest trend to tackle this issue is data-task migration and processing in or near memory.
Goal
The goal of this project is to implement dynamic data migration into a trace-based simulator and to evaluate its potential.
Prerequisites
To successfully complete this project, you should already have the following skills and experiences.
- Very good programming skills in C++ or SystemC
- Good comprehension of a complex system
- Very good knowledge about hardware development.
Contact
Sven Rheindt, Room: N2140, Phone +49.89.289.28387, sven.rheindt@tum.de
Betreuer:
Laufende Arbeiten

Exploring the Dynamicity of Region Based Cache Coherence for Distributed Shared Memory MPSoCs on an FPGA Prototype
Exploring the Dynamicity of Region Based Cache Coherence for Distributed Shared Memory MPSoCs on an FPGA Prototype
Stichworte:
Cache Coherence, Distributed Shared Memory MPSoCs
Kurzbeschreibung:
The goal of this project is to explore the dynamicity of RBCC and minimize the context switching penalties.
Beschreibung
Providing hardware coherence for modern tile-based MPSoCs requires additional area. As a result, this does not scale with increasing tile counts. As part of the Invasive Computing project, we introduced Region Based Cache Coherence (RBCC) which is a scalable approach that provides on-demand coherence. RBCC enables users to dynamically create/destroy coherency regions based on application requirements. With such dynamicity, the associated context switching overheads like cache flushing, directory flushing, coherency region reconfigurations, etc. need to be investigated and optimized.
Towards this goal you’ll complete the following tasks:
• Investigate existing directory based cache coherence schemes
• Implement/Modify a dynamic framework for RBCC
• Verify the design on a FPGA-based hardware platform
Voraussetzungen
To successfully complete this project, you should already have the following skills and experiences:
• Very Good VHDL Skills
• Good C/C++ Skills
• Good understanding of MPSoCs and Cache Coherence Schemes
• Self-motivated and structured work style
Kontakt
Akshay Srivatsa
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 22963
srivatsa.akshay@tum.de
www.lis.ei.tum.de
Betreuer:

Design and Implementation of a Fault-Tolerant Low-Throughput Broadcast Control & Management Network for System on Chip
Design and Implementation of a Fault-Tolerant Low-Throughput Broadcast Control & Management Network for System on Chip
Beschreibung
Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
One way of organizing the access to such a NoC is by using Time-Division Multiplexing (TDM) which
allows to give service guarantees. However, such a TDM NoC must be configured before it can be used which requires a reliable configuration network.
Goal
The goal of this thesis is to implement a reliable broadcast configuration network that can be used to configure the routers and network interfaces of a TDM NoC and to create tests to validate the implemented hardware.
Voraussetzungen
To successfully complete this project, you should already have the following skills and experiences:
- Good programming skills in a hardware description language i.e. VHDL or (System)Verilog
- Good knowledge of on-chip communication
- Solid Python programming skills
- At least basic knowledge of the functionality of NoCs
- Self-motivated and structured work style
Learning Objectives
By completing this project, you will be able to
- understand the concept of TDM NoCs
- create and extend hardware modules in SystemVerilog
- create tests to validate hardware modules
- document your work in form of a scientific report and a presentation
Kontakt
Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de
Betreuer:

Design and Implementation of a Network Interface for a Fault-Tolerant Hybrid Network on Chip
Design and Implementation of a Network Interface for a Fault-Tolerant Hybrid Network on Chip
Beschreibung
Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
In order to implement a safety-critical real-time application on such an MPSoC, the NoC must fulfill certain requirements: it must ensure that no critical data gets lost, all critical data gets delivered within a certain deadline, and other applications cannot interfere with the critical application. And all this must be guaranteed even in case of a fault in the NoC.
Goal
The goal of this thesis is to implement a Network Interface for a hybrid Time-Division Multiplexed (TDM) and packet-switched NoC that provides protection switching for critical traffic and to create tests to validate the behavior of the implemented hardware.
Voraussetzungen
To successfully complete this project, you should already have the following skills and experiences:
- Very good programming skills in a hardware description language i.e. VHDL or (System)Verilog
- Solid Python programming skills
- At least basic knowledge of the functionality of NoCs
- Self-motivated and structured work style
Learning Objectives
By completing this project, you will be able to
- Understand the concept of TDM NoCs
- Design and implement a complex hardware module in SystemVerilog
- Create tests to validate hardware modules
- Document your work in form of a scientific report and a presentation
Kontakt
Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de