Master's Theses
Simulationsbasierte Kameraentwicklung für autonomes Fahren (bei BMW)
Simulationsbasierte Kameraentwicklung für autonomes Fahren (bei BMW)
Description
Die BMW Group bietet dir eine interessante Studienabschlussarbeit im Bereich der Entwicklung von Kameratechnologien für das autonome Fahren. Um alltäglich in allen Situationen zuverlässig verwertbare Daten sammeln zu können, werden extreme Anforderungen an die verwendeten Kameras gestellt. Daher ist eine Optimierung aller Kamerakomponenten notwendig.
Was erwartet dich?
- Zur Erweiterung einer simulationsbasierten Entwicklungsumgebung führst du zunächst eine Literaturrecherche zu Verfahren der Optiksimulation und aktuellen Benchmark-Anwendungen der Computer Vision durch.
- Darauf stützend, analysierst du bestehende Kameratechnologien und erarbeitest eigenverantwortlich Verbesserungsvorschläge in Bezug auf einzelne technologische Parameter.
- Die Analyse und Bewertung deines neuen Kamerakonzepts schließen dein spannendes Aufgabengebiet ab.
Der Einsatz mit einer Dauer von 6 Monaten kann frühestens am 01.07.2019 beginnen.
Arbeitszeit: Vollzeit
Prerequisites
Qualifikationen und Erfahrung
- Studium der Elektrotechnik, Informatik, Fahrzeugtechnik oder ein vergleichbarer Studiengang.
- Erste praktische Erfahrung in der Programmierung mit MATLAB.
- Erweiterte Kenntnisse in den Bereichen Bildsensortechnologien und digitale Bildverarbeitung.
- Kenntnisse über aktuelle Computer Vision Verfahren.
- Sicherer Umgang mit MS Office.
- Verhandlungssichere Deutsch- und Englischkenntnisse.
- Analytisches Denkvermögen.
Contact
BMW Group Recruiting Team
+49 89 382-17001
Supervisor:
Dynamic ROI size adaptation to increase frame rates of high speed 3D laser line scanners (at SmartRay GmbH in Wolfratshausen)
Dynamic ROI size adaptation to increase frame rates of high speed 3D laser line scanners (at SmartRay GmbH in Wolfratshausen)
Description
About SmartRay
SmartRay is specialized in 3D Sensors for inspection, guidance and measurement that help manufacturing companies to improve product quality, guide automation and reduce production costs. By focusing on 3D, SmartRay has built a comprehensive portfolio of products designed to solve a rapidly increasing range of industrial applications.
Task description:
SmartRay’s laser line scanners work on the principle of laser triangulation and use a CMOS camera chip in the receive path. To achieve high scanning rates of up to 10kHz, the regions of interest (ROIs) of the camera chip are configured to only capture the laser line. However, for applications in which the object that is being scanned is not known beforehand, the optimal size of the ROIs must be determined with an automated mechanism.
In this master’s thesis, different concepts for automatic laser line tracking and the calculation of optimal ROIs should be developed. These concepts should then be evaluated and compared against each other. Afterwards, the most promising concept should be implemented as Hardware/Software Codesign in an FPGA and an ARM processor respectively.
Prerequisites
Your profile:
- Bachelor’s degree in electrical engineering, computer science, information technology, or any comparable course of studies
- Hardware description languages Verilog or SystemVerilog
- Programming languages C and C++
- Experience with Intel/Altera FPGA Design Flow is an advantage
- Experience in image and video processing is an advantage
- Good English language skills
Contact
Do you meet these requirements and want to submit an application? We look forward to hearing from you! Please send us a comprehensive application, including earliest possible starting date via email to: bewerbung@smartray.de Contact: Stefanie Ostermeier
https://www.smartray.com/company/careers/candidate-for-masters-thesis-in-fpga-engineering-f-m-d/
Supervisor:
Design of a RISC-V MPSoC with Autonomic Layer (IPF)
Design of a RISC-V MPSoC with Autonomic Layer (IPF)
Keywords:
RISC-V, MPSoC, LCT, Machine Learning, VHDL
Description
Today's Multi-Processor System-on-Chip (MPSoCs) are getting more and more complex due to the growing amount of cores and accelerators. Hence it's not possible anymore to set runtime parameters like frequency and task distribution by design time in an optimal manner. Therefore future controllers try to make use of machine learning which is aware of the system's current state (self-awareness).
Information Processing Factoriy (IPF) is a global project that claims to show self-awareness across multiple abstraction levels. It represents a paradigm shift in platform design by envisioning the move towards a consistent platform-centric design in which the combination of self-organized learning and formal reactive methods guarantee the applicability of such cyber-physical systems in safety-critical and high-availability applications.
At TUM, we explore the application and implementation of machine learning algorithms in hardware to optimize the mode of operation of MPSoCs at runtime.
Currently we use a Leon3 setup, but more and more of recent research on SoC design including CPUs is done using the open RISC V instruction set. Due to this fact the community and the amount of available tools is constantly increasing, which is a significant advantage over other platforms like SparcV8.
For this reason we want to port our current Leon3 design to this new platform.
Towards this goal the following tasks need to be done in this master thesis:
1. There exist several open source implementations of RISC V Cores which need to be compared in a first step.
2. Afterwards, a first MPSoC needs to be synthesized using the most promising implementation. A first goal on this MPSoC is to run a simple ‘Hello World’ using all cores.
3. The final step afterwards would be to attach our autonomic machine learning layer to this MPSoC in order to get a self-aware system doing DVFS and task migration autonomously.
Prerequisites
To successfully complete this project, you should already have the following skills and experiences:
• Good VHDL and Verilog Skills
• Basic Knowledge of RISC V specialities
• Good Understanding of MPSoCs
• Self-motivated and structured work style
• opional: Basic Knowledge of Machine Learning
Contact
Florian Maurer
Chair of Integrated Systems
Arcisstrasse 21,
80333 Munich
Germany
Tel. +49 89 289 23870
flo.maurer@tum.de
www.lis.ei.tum.de
Supervisor:
Development of a Concept to Enable Access to Heavily Shared Resources in an MPSoC Featuring a Hybrid NoC
Development of a Concept to Enable Access to Heavily Shared Resources in an MPSoC Featuring a Hybrid NoC
Description
Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
One way of organizing the access to such a NoC is by using Time-Division Multiplexing (TDM) which allows to give service guarantees. However, in a TDM NoC the number of parallel accesses to a resource is limited which is problematic for heavily shared resources such as memory and I/O.
Goal
The goal of this thesis is to develop a concept to enable access to heavily shared resources for critical applica tions using TDM traffic in a hybrid TDM and packet-switched NoC.
Prerequisites
To successfully complete this project, you should already have the following skills and experiences:
- Good programming skills in a hardware description language i.e. (System)Verilog or VHDL
- Good knowledge of on-chip communication
- Solid Python programming skills
- At least basic knowledge of the functionality of NoCs
- Self-motivated and structured work style
Learning Objectives
By completing this project, you will be able to
- Understand the concept of TDM NoCs
- Create and extend hardware modules in SystemVerilog
- Create tests to validate hardware modules
- Document your work in form of a scientific report and a presentation
Contact
Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de
Supervisor:
Laufende Arbeiten
Master's Theses
Exploring the Dynamicity of Region Based Cache Coherence for Distributed Shared Memory MPSoCs on an FPGA Prototype
Exploring the Dynamicity of Region Based Cache Coherence for Distributed Shared Memory MPSoCs on an FPGA Prototype
Keywords:
Cache Coherence, Distributed Shared Memory MPSoCs
Short Description:
The goal of this project is to explore the dynamicity of RBCC and minimize the context switching penalties.
Description
Providing hardware coherence for modern tile-based MPSoCs requires additional area. As a result, this does not scale with increasing tile counts. As part of the Invasive Computing project, we introduced Region Based Cache Coherence (RBCC) which is a scalable approach that provides on-demand coherence. RBCC enables users to dynamically create/destroy coherency regions based on application requirements. With such dynamicity, the associated context switching overheads like cache flushing, directory flushing, coherency region reconfigurations, etc. need to be investigated and optimized.
Towards this goal you’ll complete the following tasks:
• Investigate existing directory based cache coherence schemes
• Implement/Modify a dynamic framework for RBCC
• Verify the design on a FPGA-based hardware platform
Prerequisites
To successfully complete this project, you should already have the following skills and experiences:
• Very Good VHDL Skills
• Good C/C++ Skills
• Good understanding of MPSoCs and Cache Coherence Schemes
• Self-motivated and structured work style
Contact
Akshay Srivatsa
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 22963
srivatsa.akshay@tum.de
www.lis.ei.tum.de
Supervisor:
Design and Implementation of a Fault-Tolerant Low-Throughput Broadcast Control & Management Network for System on Chip
Design and Implementation of a Fault-Tolerant Low-Throughput Broadcast Control & Management Network for System on Chip
Description
Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
One way of organizing the access to such a NoC is by using Time-Division Multiplexing (TDM) which
allows to give service guarantees. However, such a TDM NoC must be configured before it can be used which requires a reliable configuration network.
Goal
The goal of this thesis is to implement a reliable broadcast configuration network that can be used to configure the routers and network interfaces of a TDM NoC and to create tests to validate the implemented hardware.
Prerequisites
To successfully complete this project, you should already have the following skills and experiences:
- Good programming skills in a hardware description language i.e. VHDL or (System)Verilog
- Good knowledge of on-chip communication
- Solid Python programming skills
- At least basic knowledge of the functionality of NoCs
- Self-motivated and structured work style
Learning Objectives
By completing this project, you will be able to
- understand the concept of TDM NoCs
- create and extend hardware modules in SystemVerilog
- create tests to validate hardware modules
- document your work in form of a scientific report and a presentation
Contact
Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de
Supervisor:
Design and Implementation of a Network Interface for a Fault-Tolerant Hybrid Network on Chip
Design and Implementation of a Network Interface for a Fault-Tolerant Hybrid Network on Chip
Description
Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
In order to implement a safety-critical real-time application on such an MPSoC, the NoC must fulfill certain requirements: it must ensure that no critical data gets lost, all critical data gets delivered within a certain deadline, and other applications cannot interfere with the critical application. And all this must be guaranteed even in case of a fault in the NoC.
Goal
The goal of this thesis is to implement a Network Interface for a hybrid Time-Division Multiplexed (TDM) and packet-switched NoC that provides protection switching for critical traffic and to create tests to validate the behavior of the implemented hardware.
Prerequisites
To successfully complete this project, you should already have the following skills and experiences:
- Very good programming skills in a hardware description language i.e. VHDL or (System)Verilog
- Solid Python programming skills
- At least basic knowledge of the functionality of NoCs
- Self-motivated and structured work style
Learning Objectives
By completing this project, you will be able to
- Understand the concept of TDM NoCs
- Design and implement a complex hardware module in SystemVerilog
- Create tests to validate hardware modules
- Document your work in form of a scientific report and a presentation
Contact
Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de
Supervisor:
Interference Channel Analysis (at GE Aviation)
Interference Channel Analysis (at GE Aviation)
Description
This work is an offer of General Electric Aviation supervised at TUM LIS.
About GE Aviation
GE Aviation Munich is a R&D center of excellence and is in the heart of southern Germany, on the Garching campus of the Technical University of Munich. This creates a unique blend for our engineers to be in a university setting, while performing research and development in a world-class industrial environment that is dedicated to bringing innovative technologies to market. Within the R&D community, the center maintains close partnerships with numerous universities, research institutions and technology companies in Germany and abroad.
Role summary
GE Aviation is investigating the use of modern multi-core architectures. You will characterize the interference channels of two different multi-core architectures (NXP T1040 and Xilinx Zynq Ultrascale+). The former is a quadcore Power PC built around the e5500 core, the latter a quad-core ARM built around the A53 core. This work can be done either as a student job or for your master thesis.
Responsibilities
- Enhance an existing bare-metal test suite
- Develop a test plan
- Characterize interference channels by investigating performance and determinism
- Develop and implement mitigation concepts
Expected Qualifications
- Good C/C++ Skills
- Good understanding of MPSoCs and CPU architectures
- Experience with embedded software development
- Self-motivated, structured work style and good communication skills
- Fluency in English
- Good academic track record
Contact
Supervisor at GE Aviation: Alexander Walsch