Studentische Hilfskräfte

Software Partitioning and Scheduling (at GE Aviation)

Software Partitioning and Scheduling (at GE Aviation)

Beschreibung

This work is an offer of General Electric Aviation supervised at TUM LIS.

About GE Aviation

GE Aviation Munich is a R&D center of excellence and is in the heart of southern Germany, on the Garching campus of the Technical University of Munich. This creates a unique blend for our engineers to be in a university setting, while performing research and development in a world-class industrial environment that is dedicated to bringing innovative technologies to market. Within the R&D community, the center maintains close partnerships with numerous universities, research institutions and technology companies in Germany and abroad.

Role summary

GE Aviation is investigating the use of modern multi-core architectures. You will migrate existing singlecore software to a multi-core platform. This work focuses on partitioning of existing software, deployment and schedule synthesis to maximize processor utilization. This work can be done either as a student job or for your master thesis.

Responsibilities

  • Determine tasks that can be run in parallel without impacting data flow and introducing data latency.
  • Develop an automated method for partitioning, deployment and scheduling based on a variety of
    tools.
  • Demonstrate scalability, usability and determinismof the selected solution.

Expected Qualifications

  • Good Java/C/C++ Skills
  • Good understanding of task scheduling
  • First experience with development of toolchains
  • Self-motivated, structured work style and good communication skills
  • Fluency in English
  • Good academic track record

Kontakt

Supervisor at GE Aviation: Alexander Walsch

Online application form

Betreuer:

Development of a Monitoring & Fault Injection Infrastructure for an MPSoC Demonstrator Featuring a Hybrid NoC

Development of a Monitoring & Fault Injection Infrastructure for an MPSoC Demonstrator Featuring a Hybrid NoC

Beschreibung

Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
For an MPSoC based demonstrator that is intended to demonstrate fail-operational capabilities (e.g. for automotive use cases) it is necessary to not only monitor and display the current state of the system but also inject faults into the system as well.

Goal

The goal of this work is to develop an infrastructure to monitor the traffic load and task execution in an MPSoC on an FPGA, inject faults in the system’s NoC, and provide a GUI on a host PC to display the system’s status and control the fault injection. This work can be split in several work packets.

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences:

  • Good programming skills in either a hardware description language i.e. (System)Verilog or VHDL and/or C and JavaScript (or another programming language of your choice to create a GUI)
  • Solid Python programming skills
  • At least basic knowledge of the functionality of NoCs
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • Understand the concept of TDM NoCs
  • Create and extend hardware modules in SystemVerilog
  • Create tests to validate hardware modules
  • Create and extend software on a host PC that communicates with hardware modules on an FPGA
  • Document your work in form of a scientific report and a presentation

 

 

Kontakt

Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de

Betreuer:

Interference Channel Analysis (at GE Aviation)

Interference Channel Analysis (at GE Aviation)

Beschreibung

This work is an offer of General Electric Aviation supervised at TUM LIS.

About GE Aviation

GE Aviation Munich is a R&D center of excellence and is in the heart of southern Germany, on the Garching campus of the Technical University of Munich. This creates a unique blend for our engineers to be in a university setting, while performing research and development in a world-class industrial environment that is dedicated to bringing innovative technologies to market. Within the R&D community, the center maintains close partnerships with numerous universities, research institutions and technology companies in Germany and abroad.

Role summary

GE Aviation is investigating the use of modern multi-core architectures. You will characterize the interference channels of two different multi-core architectures (NXP T1040 and Xilinx Zynq Ultrascale+). The former is a quadcore Power PC built around the e5500 core, the latter a quad-core ARM built around the A53 core. This work can be done either as a student job or for your master thesis.

Responsibilities

  • Enhance an existing bare-metal test suite
  • Develop a test plan
  • Characterize interference channels by investigating performance and determinism
  • Develop and implement mitigation concepts

Expected Qualifications

  • Good C/C++ Skills
  • Good understanding of MPSoCs and CPU architectures
  • Experience with embedded software development
  • Self-motivated, structured work style and good communication skills
  • Fluency in English
  • Good academic track record

Kontakt

Supervisor at GE Aviation: Alexander Walsch

Online application form

Betreuer:

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