Accepted papers at NOCS, MCSoC, MEMSYS, and EUROP4 2019
We received the acceptance for several papers at different conferences:
13th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2019, Oct. 17-18, 2019 in New York, USA)
- "APEC: Improved Acknowledgement Prioritization through Erasure Coding in Bufferless NoCs" authored by Michael Vonbun, Adrian Schiechel, Nguyen Anh Vu Doan, Thomas Wild, and Andreas Herkersdorf has been accepted for publication. The paper proposes adding a prioritization mechanism to ACK/NACK signals in bufferless NoCs to improve network latency, and the use of erasure coding so that dropped flits due to collision with ACK/NACK can be recovered.
- "Channel Mapping Strategies for Effective Protection Switching in Fail-Operational Hard Real-Time NoCs" authored by Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, and Andreas Herkersdorf has been accepted for the poster session, with proceeding. The paper introduces mapping strategies of channels in a fail-operational hard real-time hybrid NoC in order to maximize the NoC utilization while meeting the bandwidth requirements of critical traffic.
IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2019, Oct. 1-4, 2019 in Singapore)
- "Multicore Power Estimation using Independent Component Analysis based Modeling" authored by Mark Sagi, Nguyen Anh Vu Doan, Thomas Wild, and Andreas Herkersdorf has been accepted for publication for the Special Session on Low-power Solutions for Future SoC design. The papers proposes to use Independent Component Analysis in order the reduce the collinearity between performance counters which facilitates power estimation modeling and would enable modeling at runtime.
International Symposium on Memory Systems (MEMSYS 2019, Sept. 30 - Oct. 3 in Washington, DC, USA)
- "NEMESYS: Near-Memory Graph Copy Enhanced System-Software" authored by Sven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Thomas Wild, and Andreas Herkersdorf has been accepted for publication. The paper proposes to integrate near-memory and near-cache graph (copy) accelerators into an architecture-aware system-software. This synergy provides a performant and scalable solution to mitigate the locality wall. This work is in cooperation with the Programming paradigms group - IPD Snelting from the Karlsruhe Institute of Technology.
2nd P4 Workshop in Europe (EUROP4, Sept. 23, 2019 in Cambridge, UK)
- "Cryptographic Hashing in P4 Data Planes" authored by Dominik Scholz, Andreas Oeldemann, Fabien Geyer, Sebastian Gallenmüller, Henning Stubbe, Thomas Wild, Andreas Herkersdorf, and Georg Carle has been accepted for publication. The paper makes the case for the integration of cryptographic hash functions into programmable network data planes such as P4 and presents an extensive performance evaluation for CPU, NPU, and FPGA prototype implementations. This work is in a cooperation with the Chair of Network Architectures and Services.