Andreas Oeldemann, M.Sc.

Research Associate

Technische Universität München
Department of Electrical and Computer Engineering
Chair of Integrated Systems
Arcisstr. 21
80290 München
Germany

Phone: +49.89.289.22962
Fax: +49.89.289.28323
Building: N1 (Theresienstr. 90)
Room: N2137
Email: andreas.oeldemann@tum.de

Welcome to my website at the Chair of Integrated Systems!

I am an electrical engineer with a strong background in computer architecture, computer networks and FPGA hardware design. As a member of the LIS scientific staff, I am currently working towards a PhD degree. My research primarily focuses on low-latency, resource- and energy-efficient packet processing in modern (data center) networks. If you are interested to find out more about my work, please have a look at my research description below.

I am permanently looking for skilled students, who share my interests in network processing and would like to join my research project as part of their studies towards a Master's or Bachelor's degree. Feel free to get in touch with me via phone, e-mail or just stop by at my office.

Curriculum Vitae

  • Working towards my PhD at LIS since 2014
  • Got my Bachelor's and Master's degree in Electrical Engineering both at TUM
  • Working student positions at Infineon and Intel Mobile Communications during my studies

Teaching

Advised Theses

  • Integration of Security Functions into an FPGA-based P4 Network Processing Pipeline
    (Master's Thesis, Fabian Pusch, 2018)
  • Design and Implementation of an FPGA-based Network Interface Card using the Coherent Accelerator Processor Interface
    (Master's Thesis, Malavika Krishnaswamy, 2018)
  • Entwurf und Implementierung eines FPGA basierten Transceivers
    (External Bachelor's Thesis, Batuhan Kurunc, 2018)
  • Extending a simulation model of a load management layer to take offload decisions based on latency predictions
    (Research Internship, Spyridon Poursalidis, 2018)
  • Software-Defined Network Packet Classification on FPGAs
    (External Master's Thesis, Goekhan Kaplayan, 2017)
  • Load Management for Stateful Virtualized Network Functions
    (Research Internship, Yanqin Li, 2017)
  • Extension of an FPGA-based network tester to support continuous replay of large network traces
    (Bachelor's Thesis, Stefan Keller, 2017)
  • Untersuchung der Energieeffizienz von Data Plane Development Kit Netzwerkapplikationen
    (Bachelor's Thesis, Thomas Göttsberger, 2017)
  • Increasing the resource consumption efficiency of an FPGA-based network tester to expand the generation of traffic patterns
    (Bachelor's Thesis, Spyridon Poursalidis, 2017)
  • Extension of an FPGA-based network tester to measure transient throughput and latency variations of Ethernet networks
    (Master's Thesis, Andreas Ring, 2016)
  • Design and Implementation of IP based Communication Protocol and Control Function for a Signal Generator
    (External Master's Thesis, Sudhanshu Jiteshkumar Vora, 2016)
  • Erweiterung eines FPGA-Netzwerktesters zur Generierung von TCP Traffic
    (Bachelor's Thesis, Andreas Hanus, 2016)
  • Prototype for Pre-Silicon SW-HW Co-Verification of Mobile Device Protocol Stack Drivers
    (External Master's Thesis, Sharath Chandra, 2015)

Thesis Offers

BAMAIDPFPIPHSSHK
Titel
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Extensions & Performance Benchmarks of a CAPI-based Network Interface Card

Extensions & Performance Benchmarks of a CAPI-based Network Interface Card

Beschreibung

With ever-increasing network data rates, the data transfer between network interface card (NIC) and the host system has a decisive impact on the achievable application performance. To fully exploit the host system’s CPU capacity for application processing, it is important to minimize I/O processing overheads. In this project, we want to extend the implementation and optimize the performance of an FPGA-based NIC that is connected to the host system with the Coherent Accelerator Processor Interface (CAPI) [1] for IBM POWER8 Systems.

In a previous project an initial implementation of the CAPI-based NIC was developed using the CAPI Storage, Network and Analytics Programming (SNAP) framework [2]. The goal of this project is to integrate the physical network interfaces in the design, as well as to identify and mitigate performance bottlenecks.

[1] https://developer.ibm.com/linuxonpower/capi/

[2] https://openpowerfoundation.org/blogs/capi-snap-simple-developers

Towards this goal you will complete the following tasks:

  • Analyze source code and working principles of the existing NIC implementation
  • Getting familiar with CAPI and the CAPI SNAP framework
  • Integrate an Ethernet Media Access Controller (MAC) IP core into the FPGA design
  • Benchmark throughput and latency of FPGA-to-host communication through simulations and measurements
  • Identify performance bottlenecks, propose and implement improvements
  • Extend the design to make use of multiple RX/TX queues for multi-core processing

Voraussetzungen

To successfully complete this project, you should already have several of the following skills and experiences:

  • Knowledge of a hardware description language such as Verilog and/or VHDL
  • Hands-on FPGA development experience
  • Solid C programming skills
  • Proficiency using Linux
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • understand the basic working principles of NICs, as well as FPGA-host communication mechanisms
  • apply your theoretical knowledge to an implementation consisting of both hard- and software parts
  • document work in a scientific report form and in a presentation

Kontakt

Andreas Oeldemann
Room N2137
Tel. 089 289 22962
andreas.oeldemann@tum.de

The thesis is carried out in cooperation with

Power Systems Acceleration Department
IBM Systems – HW Development Böblingen
IBM Deutschland R&D GmbH

 

 

Betreuer:

Ongoing Theses

Publications

  • Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf: FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet. International Conference on Field-Programmable Logic and Applications (FPL), 2018 mehr… BibTeX
  • Andreas Oeldemann, Thomas Wild, Andreas Herkersdorf: Reducing Data Center Resource Over-Provisioning Through Dynamic Load Management for Virtualized Network Functions. International Conference on Architecture of Computing Systems, 2017 mehr… BibTeX Volltext ( DOI )
  • Michael Vonbun, Stefan Wallentowitz, Andreas Oeldemann, Andreas Herkersdorf: An Analytic Approach on End-to-end Packet Error Rate Estimation for Network-on-Chip. Euromicro Conference on Digital System Design (DSD), 2015 mehr… BibTeX