Assigned Topics

Bachelor's Theses

Design of a HW-Debugger for a self-aware SoC paradigm based on hardware machine learning (IPF)

Design of a HW-Debugger for a self-aware SoC paradigm based on hardware machine learning (IPF)

Keywords:
Machine Learning, Supervisory control theory, Learning Classifier system, HW Debugger, VHDL, SoC, C, Matlab

Short Description:
The goal of this project is to develop a hardware debugger for the machine learning based IPF platform.

Description

Today's Multi-Processor System-on-Chip (MPSoCs) are getting more and more complex due to the growing amount of cores and accelerators.  Hence it's not possible anymore to set runtime parameters like frequency and task distribution by design time in an optimal manner. Therefore future controllers try to make use of machine learning which is aware of the system's current state (self-awareness).

Information Processing Factoriy (IPF) is a global project that claims to show self-awareness across multiple abstraction levels. It represents a paradigm shift in platform design by envisioning the move towards a consistent platform-centric design in which the combination of self-organized learning and formal reactive methods guarantee the applicability of such cyber-physical systems in safety-critical and high-availability applications.

At TUM, we explore the application and implementation of machine learning algorithms in hardware to optimize the mode of operation of MPSoCs at runtime. 

Towards this goal, you'll complete the following tasks:
1. Understand the current implementation of Learning Classifier Tables (LCT) and Supervisory Control as well as their communication with SW and our GUI in VHDL.
2. Design and implement a new HW debugger, which can provide measurement values at a higher rate than the current SW debugger and which doesn't interfere with benchmarks executed on the cores.
3. Verify the interplay between GUI and your HW debugger.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences:
• Good VHDL Skills
• Good C / C ++ Skills
• Good Matlab Skills
• Good Understanding of MPSoCs
• Self-motivated and structured work style
• opional: basic knowledge of machine learning

Contact

Florian Maurer
Chair of Integrated Systems 
Arcisstrasse 21, 80333 Munich Germany
Tel. +49 89 289 23870 
flo.maurer@tum.de
www.lis.ei.tum.de

 

Anmol Prakash Surhonne
Chair of Integrated Systems
Arcisstrasse 21, 80333 Munich Germany
Tel. +49 89 289 23872
anmol.surhonne@tum.de
www.lis.ei.tum.de 

Supervisor:

Florian Maurer, Anmol Prakash Surhonne

Development of a Monitoring & Fault Injection Infrastructure for an MPSoC Demonstrator Featuring a Hybrid NoC

Development of a Monitoring & Fault Injection Infrastructure for an MPSoC Demonstrator Featuring a Hybrid NoC

Description

Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
For an MPSoC based demonstrator that is intended to demonstrate fail-operational capabilities (e.g. for automotive use cases) it is necessary to not only monitor and display the current state of the system but also inject faults into the system as well.

Goal

The goal of this work is to develop an infrastructure to monitor the traffic load and task execution in an MPSoC on an FPGA, inject faults in the system’s NoC, and provide a GUI on a host PC to display the system’s status and control the fault injection. This work can be split in several work packets.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences:

  • Good programming skills in either a hardware description language i.e. (System)Verilog or VHDL and/or C and JavaScript (or another programming language of your choice to create a GUI)
  • Solid Python programming skills
  • At least basic knowledge of the functionality of NoCs
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • Understand the concept of TDM NoCs
  • Create and extend hardware modules in SystemVerilog
  • Create tests to validate hardware modules
  • Create and extend software on a host PC that communicates with hardware modules on an FPGA
  • Document your work in form of a scientific report and a presentation

 

 

Contact

Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de

Supervisor:

Development of an I/O Tile for an MPSoC Demonstrator Featuring a Hybrid TDM and Packet-Switched NoC

Development of an I/O Tile for an MPSoC Demonstrator Featuring a Hybrid TDM and Packet-Switched NoC

Description

Enabled by ever decreasing structure sizes, modern System on Chips (SoC) integrate a large amount of different processing elements, making them Multi-Processor System on Chips (MPSoC). These processing elements require a communication infrastructure to exchange data with each other and with shared resources such as memory and I/O ports. The limited scalability of bus-based solutions has led to a paradigm shift towards Network on Chips (NoC) which allow for multiple data streams between different nodes to be exchanged in parallel.
Each SoC also needs a way to communicate with its environment, typically provided in form of an I/O tile. For an MPSoC demonstrator on an FPGA it is necessary to implement such an I/O tile to enable data exchange between the applications running on the FPGA and a host PC.

Goal

The goal of this work is to implement an I/O tile for an MPSoC demonstrator on an FPGA and enable data exchange between the applications running on the FPGA and a host PC.

Prerequisites

To successfully complete this project, you should already have the following skills and experiences:

  • Good programming skills in a hardware description language i.e. (System)Verilog or VHDL
  • Good programming skills in C
  • Solid Python programming skills
  • At least basic knowledge of the functionality of NoCs
  • Self-motivated and structured work style

Learning Objectives

By completing this project, you will be able to

  • Understand the concept of TDM NoCs
  • Create and extend hardware modules in SystemVerilog
  • Create tests to validate hardware modules
  • Document your work in form of a scientific report and a presentation

 

 

Contact

Max Koenen
Room N2118
Tel. 089 289 23084
max.koenen@tum.de

Supervisor: