Forschungspraxis oder MSCE Forschungspraxis

Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype

Extending Region Based Cache Coherence to Global (DDR) Memory for Distributed Shared MPSoCs on an FPGA Prototype

Stichworte:
Cache Coherence, Distributed Shared Memory MPSoCs

Kurzbeschreibung:
The goal of this project is to extend RBCC to global memory with distributed directories.

Beschreibung

Providing hardware coherence formoderntile-based MPSoCsrequires additional area. As a result, this does not scale with increasing tile counts.As part of the Invasive Computing project, we introducedRegion Based Cache Coherence (RBCC) whichis ascalableapproachthat provides on-demand coherence. RBCC enables users to dynamically create/destroy coherency regions based on application requirements. Currently, RBCC has been developed for the distributed tile local memories of our system. The next step is to extend RBCC to the global memory, so as to fully utilize the memory capacity of our heterogeneous muticore architecture.

Towards this goal you’ll complete the following tasks:

  • Investigate existing distributed directory based cache coherence schemes

  • Extend RBCC to global DDR memory

  • Verify the design on a FPGA-based hardware platform

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences.

  • Very Good VHDL Skills

  • Good C/C++ Skills

  • Good understanding of MPSoCs and Cache Coherence Schemes

  • Self-motivated and structured work style

 

 

Kontakt

Akshay Srivatsa
Chair of Integrated Systems
Arcisstraße 21, 80333 Munich
Tel. +49 89 289 22963
srivatsa.akshay@tum.de
www.lis.ei.tum.de

Betreuer:

Assigned Topics

Forschungspraxis oder MSCE Forschungspraxis

HW-SW interface design for a self-aware SoC paradigm based on hardware machine learning (IPF)

HW-SW interface design for a self-aware SoC paradigm based on hardware machine learning (IPF)

Stichworte:
Machine Learning, Supervisory control theory, Learning Classifier system, HW-SW Interface, VHDL, C, SoC

Kurzbeschreibung:
The goal of this project is to develop a hardware-software interface for the machine learning based IPF platform.

Beschreibung

As today's Multi-Processor System-on-Chip (MPSoCs) are getting more and more complex due to the growing amount of cores and accelerators.  Hence it's not possible anymore to set runtime parameters like frequency and task distribution by design time in an optimal manner. Therefore future controllers try to make use of machine learning which is aware of the system's current state (self-awareness).

Information Processing Factoriy (IPF) is a global project that claims to show self-awareness across multiple abstraction levels. It represents a paradigm shift in platform design by envisioning the move towards a consistent platform-centric design in which the combination of self-organized learning and formal reactive methods guarantee the applicability of such cyber-physical systems in safety-critical and high-availability applications.

At TUM, we explore the application and implementation of machine learning algorithms in hardware to optimize the mode of operation of MPSoCs at runtime. 

Towards this goal, you'll complete the following tasks:
1. Understand the current implementation of Learning Classifier Tables (LCT) and Supervisory Control as well as their communication with SW in VHDL.
2. Design and implement a new HW-SW interface which supports new features and functionalities on the FPGA.
3. Develop a software API to utilize the functionalities implemented in hardware.
4. Test your new HW-SW interface.

Voraussetzungen

To successfully complete this project, you should already have the following skills and experiences:
• Good VHDL Skills
• Good C / C ++ Skills
• Good Understanding of MPSoCs
• Self-motivated and structured work style
• opional: basic knowledge of machine learning

Kontakt

Anmol Prakash Surhonne
Chair of Integrated Systems
Arcisstrasse 21, 80333 Munich Germany
Tel. +49 89 289 23872
anmol.surhonne@tum.de
www.lis.ei.tum.de 

Florian Maurer
Chair of Integrated Systems
Arcisstrasse 21, 80333 Munich Germany
Tel. +49 89 289 23870
flo.maurer@tum.de
www.lis.ei.tum.de

Betreuer:

Anmol Prakash Surhonne, Florian Maurer